Does the ET4000/W32 use multiple IRQ lines? Or just a single one that's shared accross functions of it?

I know of two interrupt sources it generates so far:
- Either vertical retrace starting or CRTC/Sprite interrupts: signalled on the normal VGA interrupt? Setup for IRQ 11 in UniPCemu? Reported in the normal EGA-compatible way, also used to clear it, using the EGA/VGA registers.
- ACL(Accelerator) interrupts, signalled on the very same VGA interrupt? Also setup for IRQ 11 in UniPCemu? Reported using the ACL registers instead of the VGA-compatible registers.
It's at IRQ 11 instead of 9 because the IRQ9 is already used by the MPU-401, if installed (on AT architecture and up, not on XT(where it's shared with the MPU-401 IRQ 9)).

When both are raised, acnowledging either one of them through their respective registers lowers the IRQ line (the other will lower it as well, just not acknowledge it in it's registers).

Would that be correct behaviour?