Original(?) OPTi 391 has "8+1" caching interface and has DIRTY_WE and DIRTY_DATA signals, i hope theses signals already connected to U21

I am concerned by the traces on your board. It seems all 4 data pins of the 16k x 4 layout are connected to something. Possibly this is just dedicated pull-up resistors, which would be harmless. But if more than one data bit is actually used, something works different than one might expect. There is some hope: All four data pins have a trace going to the right (where the resistor networks are), but only one data pin has a trace going to the left (where the 391 chip is). This is also the the way the Opti 391 datasheet suggests to wire the dirty tag RAM at the end of the OPTi-386WB data sheet.

So it is quite likely that adapting the 24129 layout to th QS8888A layout will work to provide the dirty bit. Indeed, you can just ground /OE on the 24129.

Done, but only CACHECHK shows big difference, games and 3d benchs shows very little improvement.
OE and pin1(adress line for >=16K chips) are grounded. Something still wrong, not every SRAM chips works:
CY7C199 -15 (32K) hangs on POST code 13
W24128AK -15 (16K) hangs before BIOS detected configuration screen
KM68257BP -20(32K) OK
IS61C256 -15(32K) OK

CACHECHK results:
1) Always DIRTY

CACHECHK V5 10/6/96 Copyright (c) 1995-96 by Ray Van Tassle. (-h for help) CMOS reports: conv_mem= 640K, ext_mem= 3,072K, Tota […]
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CACHECHK V5 10/6/96 Copyright (c) 1995-96 by Ray Van Tassle. (-h for help)
CMOS reports: conv_mem= 640K, ext_mem= 3,072K, Total RAM= 3,712K
386 Clocked at 39.0 MHz
Reading from memory.
MegaByte#: --------- Memory Access Block sizes (KB)-----
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 <-- KB
0: 39 39 39 39 39 39 39 39 39 90 -- -- -- us/KB
1: 39 39 39 39 39 39 39 39 39 90 90 90 -- us/KB
2 3 <--- same as above.

Extra tests----
Wrt 33 33 33 33 33 33 33 34 33 33 33 33 --<-Writing
This machine seems to have one cache!? [reading]
>>>> If you think you do have L2 cache, you might have FAKE CACHE chips! <<<<
!! cache is 256KB -- 27.9 MB/s 37.6 ns/byte (228%) 5.6 clks
Main memory speed -- 12.2 MB/s 85.8 ns/byte (100%) [reading] 12.8 clks
Effective RAM access time (read ) is 171ns (a RAM bank is 2 bytes wide).
Effective RAM access time (write) is 63ns (a RAM bank is 2 bytes wide).
386 Clocked at 39.0 MHz. Cache ENABLED.

2) DIRTY TAG soldered

CACHECHK V5 10/6/96 Copyright (c) 1995-96 by Ray Van Tassle. (-h for help) CMOS reports: conv_mem= 640K, ext_mem= 3,072K, Tota […]
Show full quote

CACHECHK V5 10/6/96 Copyright (c) 1995-96 by Ray Van Tassle. (-h for help)
CMOS reports: conv_mem= 640K, ext_mem= 3,072K, Total RAM= 3,712K
386 Clocked at 39.0 MHz
Reading from memory.
MegaByte#: --------- Memory Access Block sizes (KB)-----
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 <-- KB
0: 39 39 39 39 39 39 39 39 39 60 -- -- -- us/KB
1: 39 39 39 39 39 39 39 39 39 60 60 60 -- us/KB
2 3 <--- same as above.

Extra tests----
Wrt 33 33 33 33 33 33 33 33 33 33 33 33 --<-Writing
This machine seems to have one cache!? [reading]
>>>> If you think you do have L2 cache, you might have FAKE CACHE chips! <<<<
!! cache is 256KB -- 27.9 MB/s 37.6 ns/byte (150%) 5.6 clks
Main memory speed -- 18.5 MB/s 56.8 ns/byte (100%) [reading] 8.4 clks
Effective RAM access time (read ) is 113ns (a RAM bank is 2 bytes wide).
Effective RAM access time (write) is 63ns (a RAM bank is 2 bytes wide).
386 Clocked at 39.0 MHz. Cache ENABLED.

Memory read speed 18.5 MB/s vs 12.2 MB/s in one synthetic test...

Edit: pin1(adress line for >=32K chips)

>games and 3d benchs shows very little improvement

only something with working set bigger than your cache would show any, Doom maybe? FastDoom?