This is a point, and one of the two regrets of the current architecture, which is the inability to achieve the read timing of 2-1-1-1 at full frequency
The original design of Pentium series L2cache had SSRAM addresses and data directly connected to the processor's tri state main interface.
At present, the voltage of the SSRAM found is 3.3V or below, while the IO of 286, 386, most 486, and P5 are 5V. Directly connecting them will damage the SSRAM chip.
Stratix's IO can tolerate 5V, so I hid the SSRAM behind the FPGA. At time zero, the processor's memory access is valid, the FPGA latches the memory access address on the rising edge and outputs it to the SSRAM.
The first rising edge SSRAM latches the address, the second rising edge SSRAM outputs the read data, and the third rising edge FPGA latches the data and tag, and compare the tag.
If it hits, the data is output, and the fourth rising edge processor takes away the L2 read data. SSRAM has four cycles, corresponding to two cycles of processor 3-1-1-1 read timing.
In one sentence, the original design of SSRAM can achieve 3-1-1-1 at the same frequency, and hiding SSRAM behind FPGA requires doubling the SSRAM frequency.
The official external frequency of SS7 is up to 100, and the frequency of SSRAM must be greater than 200. Fortunately, the highest frequency of SSRAM I found is about 250M.
If the overclocking is not too high, it is basically sufficient. To achieve the timing requirement of 2-1-1-1, the SSRAM frequency is four times that of FSB, and the external frequency of the processor does not exceed 50M.
Therefore, for 286386, the vast majority of 486, and P24T, zero overhead latency can be achieved
Another regret of this architecture is AGP4x, it transfers data 4 times per cycle, 66x4=266, which is at the same rate as DDR266. FPGA also supports 1.5V, which theoretically can be implemented with Stratix,
but more time is needed to study the spec and implement it.
The biggest problem with current hardware is that it's not fun, the choices are limited, everyone is the same, and it's boring.
This is also my original intention for designing this board. It can accommodate 20+types of processors, AGP1x/2x, and possibly even 4x graphics cards, Voodoo 1/2/3/4, Rendition, PCI S3, ISA DOS graphics cards, CGA/EGA, various PCI/ISA sound cards, PCI ATA100/SATA, USB2.0. It is capable of playing games before 2000, and I believe most people who have come from that era will have fun playing it
