_ar wrote on 2024-10-05, 12:49:

The coin cell battery and pin header for cmos clear/external battery is heavily corroded, so I have swapped them out for new ones.

locate a diode nearby (most likely a dual diode - 3 pin smd package), its likely also corroded and not passing battery to ICH

rasz_pl wrote on 2024-10-06, 03:19:

_ar wrote on 2024-10-05, 12:49:

The coin cell battery and pin header for cmos clear/external battery is heavily corroded, so I have swapped them out for new ones.

locate a diode nearby (most likely a dual diode - 3 pin smd package), its likely also corroded and not passing battery to ICH

Thanks for the reply! Here's a schematic of the area and a couple of measurements I made.

Battery Only: TP1 3.215, TP2 3.00, TP3 3.00, TP4 0.00
PSU on STANDBY: TP1 3.215, TP2 3.418, TP3 3.42 TP4 3.646
No Battery, PSU on STANDBY: TP1 0.00, TP2 3.42, TP3 3.42, TP4 3.65

There are two separate zener diodes basically, which all test fine in circuit and according to these measurements work fine as well. D1 had some corrosion on (mould) but it easily came off with IPA.

There's another zener on the board (not on the schematic) in the 'Standby PWR' part. In circuit (diode mode), it seems to be open in both directions. However, I'm not sure if that should affect this part as it's behind D2 and I have also read that zener diodes can test bad in circuit.

Do you see anything out of the ordinary here?

Since you can read schematics
https://www.gadget-manual.com/intel/

440bx reference schematic in there

Put your multimeter in micro amp mode and measure the battery current draw while psu is disconnected, it should be around 10 micro amps.

TP2 and TP3 is same thing 😀 other than that it looks fine 🙁
I assume you checked CMOS Clear jumper first 😀 and there is near infinite resistance between pins 1 and 3.
What is the resistance to ground on TP2? What was the power draw when you hooked bench supply instead of battery? If should definitely NOT be 5 or 3 * 1.5V, Chipset is low power and might not liked 5V pumped into it, Intel wants 3V there.

myne wrote on 2024-10-06, 16:35:

Since you can read schematics
https://www.gadget-manual.com/intel/

440bx reference schematic in there

Thank you!

Karbist wrote on 2024-10-06, 16:59:

Put your multimeter in micro amp mode and measure the battery current draw while psu is disconnected, it should be around 10 micro amps.

Hi, Thank you for the idea! I am measuring zero draw (0.1 uA). I have double checked my method on a 486 board where it showed 5.9 uA, so IMHO my measurement is correct, no draw at all.

rasz_pl wrote on 2024-10-06, 17:11:

TP2 and TP3 is same thing 😀 other than that it looks fine 🙁
I assume you checked CMOS Clear jumper first 😀 and there is near infinite resistance between pins 1 and 3.
What is the resistance to ground on TP2? What was the power draw when you hooked bench supply instead of battery? If should definitely NOT be 5 or 3 * 1.5V, Chipset is low power and might not liked 5V pumped into it, Intel wants 3V there.

Yes you right, TP2 is basically TP3 😀 but on the board there's the battery holder in between so I basically was testing both points just to be sure there's no breakage in the circuit.

Yes, I have tested the CMOS jumper as well. This board has a 4 pin header as it accepts an external battery (see attachment from the manual below) so I assume you were referring to pin 2 - 4, BATT + and GND. There's infinite resistance between those pins.

I have set the bench power supply's limit so that I got around 3.45 at TP2, basically matching the voltage the circuit gets when only the ATX PSU is connected. The current limit I set to 0.001A first and to 0.005A next, but the bench supply was in CV mode and showed no current draw during the test.

Was the zero draw with ATX psu unplugged? otherwise it might be simply being overridden with 3VSB
Unplug battery, desolder D2, plug your multimeter in its place, plug supply in and see if there is any draw.
No draw means either corrosion somewhere further down TP2 and PIIX4 or blown PIIX4

rasz_pl wrote on 2024-10-07, 11:49:

Was the zero draw with ATX psu unplugged? otherwise it might be simply being overridden with 3VSB
Unplug battery, desolder D2, plug your multimeter in its place, plug supply in and see if there is any draw.
No draw means either corrosion somewhere further down TP2 and PIIX4 or blown PIIX4

Yes, the zero draw was with the ATX PSU unplugged.

Instead of desoldering anything, I used my multimeter in uA mode to inject the voltage from a battery into all the test points on the schematic. Measured no draw for all test points. It's a blown PIIX4. Is it something that happens? I mean everything else works just fine ... Strange, but it is what it is then. Thank you very much for your help!

Most likely the solder joint under the chipset is corroded.

I would look for more corrosion first, unless there is 5V or 12V near the battery and previous corrosion led to 5/12 Volts going into VBATT pin.

rasz_pl wrote on 2024-10-08, 05:00:

I would look for more corrosion first, unless there is 5V or 12V near the battery and previous corrosion led to 5/12 Volts going into VBATT pin.

There were a couple of occasions, maybe like two, during my testing when the settings survived a powerdown. I was thinking, the board probably shadows the settings, like my 386DXs do, and maybe that what survived, not the nvram content. Or, as you guys say, maybe some current seeps through some corrosion sometimes somewhere and that was what kept the settings. I don't know, I'll keep an eye out for corrosion and remove it if I find anything.

BTW, here're a couple of pics after desoldering the battery holder and the cmos jumper. That diode on the last pic is D1 on my schematics, maybe I'll resolder it later.

-- EDIT, just one thing, I kept measuring around 1.5ohms of resistence when doing continuity checks, which I find odd, I would expect something like 0.5Ohms or something, I'll try to locate the source of this.

>during my testing when the settings survived a powerdown

SRAM has high retention, perfectly normal to survive maybe even up to tens of seconds.

so C2 is C154? its really dark, doesnt look too well 😀
Corrosion didnt look to bad, but VIAs can be fragile. All those VIAs under the battery dont fill me with confidence. Imo its much more likely the problem is with eaten via than the PIIX4 ball, especially considering VCC (RTC) ball location 5 rows deep. Dont see any potential 5/12 sources to bleed and blow the chip either.

Resistor immediately above crystal looks burnt.

Not the best picture though

rasz_pl wrote on 2024-10-08, 06:41:

>during my testing when the settings survived a powerdown […]
Show full quote

>during my testing when the settings survived a powerdown

SRAM has high retention, perfectly normal to survive maybe even up to tens of seconds.

so C2 is C154? its really dark, doesnt look too well 😀
Corrosion didnt look to bad, but VIAs can be fragile. All those VIAs under the battery dont fill me with confidence. Imo its much more likely the problem is with eaten via than the PIIX4 ball, especially considering VCC (RTC) ball location 5 rows deep. Dont see any potential 5/12 sources to bleed and blow the chip either.

I usually cut the power for about 5secs, so considering this, probably it really was the nvram that somehow kept its content?

Yes, C2 is C154 😀, let me attach an updated version of the schematics with the actual component names. However, C154 is behind D15, can it still cause something like this? I'll also take another look under the battery holder and check those traces.

myne wrote on 2024-10-08, 07:25:

Resistor immediately above crystal looks burnt.

Not the best picture though

Took a better one. Also C149 looks a bit wonky.

Check all caps for shorts, and resistors for open. Caps usually fall short resistors open.

On the board isn't ideal, but should be good enough.

Might be corroded, might be just super dirty.

>However, C154 is behind D15, can it still cause something like this?

no, but I suspect the VIA directly below C154 between 5 and 4 is the one going to the BGA VCCBATT and if this cap is corroded so might be the via.