Most likely Anandtech typo.

Well there's others making the exact same multi character typo then...

The Apollo-VP3 is a high performance, cost-effective and energy efficient chip set for the implementation of AGP / PCI […]
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The Apollo-VP3 is a high performance, cost-effective and energy
efficient chip set for the implementation of AGP / PCI / ISA desktop
and notebook personal computer systems based on 64-bit Socket-7 (Intel
Pentium and Pentium MMX; AMD K5 / 5k86 and K6 / 6k86; and Cyrix / IBM
6x86 / M2) super-scalar processors.

The Apollo-VP3 chip set consists of the VT82C597 system controller
(472 pin BGA) and the VT82C586B PCI to ISA bridge (208 pin PQFP). The
VT82C597 system controller provides superior performance between the
CPU, optional synchronous cache, DRAM, AGP bus, and PCI bus with
pipelined, burst, and concurrent operation. For pipelined burst
synchronous SRAMs, 3-1-1-1-1-1-1-1 timing can be achieved for both
read and write transactions at 66 MHz. Four cache lines (16
quadwords) of CPU/cache to DRAM write buffers with concurrent
write-back capability are included on chip to speed up cache read and
write miss cycles.

The VT82C597 supports six banks of DRAMs up to 1GB. The DRAM
controller supports standard Fast Page Mode (FPM) DRAM, EDO-DRAM,
Synchronous DRAM (SDRAM), and SDRAM-II with Double Data Rate (DDR) in
a flexible mix / match manner. The Synchronous DRAM interface allows
zero wait state bursting between the DRAM and the data buffers at
66Mhz. The six banks of DRAM can be composed of an arbitrary mixture
of 1M / 2M / 4M / 8M / 16MxN DRAMs. The DRAM controller also supports
optional ECC (single-bit error correction and multi-bit detection) or
EC (error checking) capability separately selectable on a bank-by-bank
basis.

The VT82C597 also supports full AGP v1.0 capability for maximum bus
utilization including 2x mode transfers, SBA (SideBand Addressing),
Flush/Fence commands, and pipelined grants. An eight level request
queue plus a four level post-write request queue with thirty-two and
sixteen quadwords of read and write data FIFO's respectively are
included for deep pipelined and split AGP transactions. A
single-level GART TLB with 16 full associative entries and flexible
CPU/AGP/PCI remapping control is also provided for operation under
protected mode operating environments.

The VT82C597 supports two 32-bit 3.3 / 5V system buses (one AGP and
one PCI) with 64-bit to 32-bit data conversion. The 82C597 also
contains a built-in bus-to-bus bridge to allow simultaneous concurrent
operations on each bus. Five levels (doublewords) of post write
buffers are included to allow for concurrent CPU and PCI operation.
Consecutive CPU addresses are converted into burst PCI cycles with
byte merging capability for optimal CPU to PCI throughput. For PCI
master operation, forty-eight levels (doublewords) of post write
buffers and sixteen levels (doublewords) of prefetch buffers are
included for concurrent PCI bus and DRAM/cache accesses. The chipset
also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize
snoop overhead. In addition, the chipset supports advanced features
such as snoop ahead, snoop filtering, L1 write-back forward to PCI
master and L1 write-back merged with PCI post write buffers to
minimize PCI master read latency and DRAM utilization. The VT82C586B
PCI to ISA bridge supports four levels (doublewords) of line buffers,
type F DMA transfers and delay transaction to allow efficient PCI bus
utilization and (PC I-2.1 compliant). The VT82C586B also includes an
integrated keyboard controller with PS2 mouse support, integrated
DS12885 style real time clock with extended 256 byte CMOS RAM,
integrated master mode enhanced IDE controller with full scatter and
gather capability and extension to UltraDMA-33 / ATA-33 for 33MB/sec
transfer rate, integrated USB interface with root hub and two function
ports with built-in physical layer transceivers, Distributed DMA
support, and OnNow / ACPI compliant advanced configuration and power
management interface. A complete main board can be implemented with
only six TTLs.

From mR_Slug http://66.113.161.23/~mR_Slug/chipset/chipset … 4&3=36001#35726

DDR standard (Jedec 2000) didnt exist when VP2 VP3 were manufactured, so they were either flying blind or using some pre production ram.

> 66MHz DDR (Double Data Rate) supported for SDRAM-II (supports central and edge DQ, bidirectional DS, and optional SDR write)

means it was useless 😀 same clock as SDR but double the latency. DDR was a big deal for VIA and they rushed it to market as soon as they could deliver 266MHz chipset with Apollo Pro266.

Yeah I thought it was gonna be preliminary, and that at the time it was not exactly unknowable spaceman tech, but was hung up in courts due to RAMbus legal skullduggery. So no consumer modules, but graphics cards were getting GDDR on them on ASIC that had a development lead time stretching back before VP3, so they must have guessed right and they seemed to have a year headstart on fully DDR motherboards.

I figured it was the same source clock, but it's same latency in real time as SDR surely, just more ticks off the edge triggered internal rate.

rasz_pl wrote on 2024-12-02, 21:08:

DDR standard (Jedec 2000) didnt exist when VP2 VP3 were manufactured, so they were either flying blind or using some pre production ram.

DDR chips being available was already announced in 1997, with delivery promised in 1998. See https://www.forbes.com/1997/07/22/glossary.html for example.This doesn't mean you date for the JEDEC standard is wrong, but clearly Samsung had preliminary designs and specification sheets in 1997, and possibly already some chips in production in 1998.

I will not take then VIA Technologies marketing department claims too seriously.
JEDEC DDR SDRAM Specification (JESD79) is dated June 2000, and considering the open system nature of the PC industry, there is no way one can ensure interoperability without the official JEDEC spec being available at the bare minimum.
Note that companies that design ASIC / ASSP often put in more features than is officially acknowledged.
They often ship ASIC / ASSP with certain features disabled by a semiconductor tester because they could not finish validating the block on time or is simply too buggy to be activated.
An example for VIA I have read somewhere is that Apollo Pro 133A (VT82C694X) and / or its Super South (VT82C686B) had the necessary circuitry to support a dual processor configuration, but they shipped it disabled for a while.
Eventually, they started to provide a dual processor configuration,.
Apparently they enabled it a year or so later after the initial release of Apollo Pro 133A.
From what I read, they "finished" the validation of the circuitry equivalent to Intel 82093AA I/O APIC controller integrated inside VT82C686B.
Note that VIA has at least 4 major revisions of VT82C686B.
That is, Version CD / CE / CF / CG marking on their package.

I think instead of considering VIA's old chipset, it's better to redesign a northbridge using DDR SDRAM with FPGA, to support the processors we want to support as much as possible, and to design a new retro motherboard with PIIX4E's southbridge

1 find the datasheets. There might be reserved register settings that hint at undocumented features.
2 is not uncommon at all for chips to have fuses built in to disable features - for a multitude of reasons. Testing new features on production chips, market segmentation (celeron), locking multipliers, fixing registers, chip ids.

It's cheaper in many ways to add a test feature to a new revision of production wafers and disable it than to do a single wafer.

3 yes, Intel, Via, AMD etc were most likely testing DDR at the time, (I seem to recall one Intel datasheet mentioning rdram earlier than I expected) and most likely the production silicon had it there.

It most likely was fused permanently and won't ever work though.

rasz_pl wrote on 2024-12-02, 21:08:

DDR standard (Jedec 2000) didnt exist when VP2 VP3 were manufactured, so they were either flying blind or using some pre production ram.

> 66MHz DDR (Double Data Rate) supported for SDRAM-II (supports central and edge DQ, bidirectional DS, and optional SDR write)

means it was useless 😀 same clock as SDR but double the latency. DDR was a big deal for VIA and they rushed it to market as soon as they could deliver 266MHz chipset with Apollo Pro266.

DDR was always same clock with multiple signals. "DDR266" was a 133MHz clock with signals on both edges.

bracecomputerlab wrote on 2024-12-03, 07:22:

JEDEC DDR SDRAM Specification (JESD79) is dated June 2000, and considering the open system nature of the PC industry, there is no way one can ensure interoperability without the official JEDEC spec being available at the bare minimum.

That date is FAR less important than you think it is. Some of us have been around long enough to have owned RAM, PC2700 for example, for MONTHS in advance of there being an official JEDEC standard for it. Most of the discussion and preliminary proposals are public and it can be seen which way things are going. Don't forget also this is not a body that says, "This is a good idea, go and do it like this." and then innovation happens, no, the members make things first and say "this is how we're doing it"

RAMbus left JEDEC in 1995, but for it to have poisoned the well for DDR with it's claimed proprietary tech, there must have been discussion of DDR features that early. I know they didn't go to court until 2000, but they were no doubt having their lawyers write nasty letters and were also demanding money with legal menaces some time before that. Therefore slowing down adaption of DDR tech through FUD. It's a late 90s tech that got slowed down by bullshit.

dionb wrote on 2024-12-03, 14:31:

rasz_pl wrote on 2024-12-02, 21:08:

DDR standard (Jedec 2000) didnt exist when VP2 VP3 were manufactured, so they were either flying blind or using some pre production ram.

> 66MHz DDR (Double Data Rate) supported for SDRAM-II (supports central and edge DQ, bidirectional DS, and optional SDR write)

means it was useless 😀 same clock as SDR but double the latency. DDR was a big deal for VIA and they rushed it to market as soon as they could deliver 266MHz chipset with Apollo Pro266.

DDR was always same clock with multiple signals. "DDR266" was a 133MHz clock with signals on both edges.

That's how marketing wanted it described some time later, bigger number gooder, but it's possible it is either way in earlier references, 66Mhz source clock for 133 internal rate, or 66Mhz internal rate for 33Mhz source.

But yeah, datasheets would be nice to see what's really up in this particular part.

Oh here we go, thought it was one of those long sought, long missing things...
https://dosdays.co.uk/media/via/VIA_82C597.pdf

I have about used up my day's ration of thinking juice or something, but am I right in thinking the DS0 to DS3 data strobes are the equivalent of DDQ, I am not sure if this made it clearer for me or put me on the wrong track... https://electronics.stackexchange.com/questio … e-in-ddr-memory

(Edit: BTW that's the real relevance of JEDEC standard, having everyone label their pins the same.)

EditII: A little more of the relevant light reading https://www.nxp.com/docs/en/application-note/AN2582.pdf