I don't recall any software control in the datasheets I have looked at, but even if there is, the signal must still be physically connected to the relevant ISA pin, there's no other way for a card to signal faster cycles than this signal.

As Tiido says, you need the proper hardware connection to get 0WS operation on ISA cards, i.e. something that drives ISA pin B8. Typically, the 0WS jumper on ET4000 cards is simlpy interrupting the line that connects to B8. I've never seen cards that have software control over interrupting that line (although it is possible to build such a thing), but a physical connection between the graphics chip and the ISA pin B08 is not the only thing you need to get 0WS operation. Furthermore, the graphics chip has to drive the pin that is connected to 0WS if a 0WS cycle is possible. AFAIK the ET4000AX does not have a dedicated "0WS" output, and most ET4000AX cards that support 0WS operation just route the generic "ET4000 chip selected" signal to the 0WS line. So I don't think any ET4000AX card will have software controlled 0WS operation.

It's different with other cards, though. AFAIK the Cirrus GD542x series has a software controllable register to configure the standard amount of wait states (0..3 on ISA, 1..4 on VL for the GD5429, 2..5 on VL for the older ones). On the Trident 8900D series, the write buffer on the card is software controllable. Without assistance of that write buffer, it can't do 0WS cycles, so disabling the write buffer will effectively disable 0WS operation, but just as a side effect. Alas, I have no knowledge about S3 chips on the ISA bus.

mkarcher wrote on 2025-01-20, 18:39:

It's different with other cards, though. AFAIK the Cirrus GD542x series has a software controllable register to configure the standard amount of wait states (0..3 on ISA, 1..4 on VL for the GD5429, 2..5 on VL for the older ones). On the Trident 8900D series, the write buffer on the card is software controllable. Without assistance of that write buffer, it can't do 0WS cycles, so disabling the write buffer will effectively disable 0WS operation, but just as a side effect. Alas, I have no knowledge about S3 chips on the ISA bus.

thanks a lot for the info, man. at least i know that its possible for cirrus, and i am considering buying a gainward cl-gd5429 with 2mb dram sockets but no 0wait jumper.
is there any ready-made programs that does this, or can i make one within a few lines of debug?

mkarcher wrote on 2025-01-20, 18:39:

On the Trident 8900D series, the write buffer on the card is software controllable. Without assistance of that write buffer, it can't do 0WS cycles, so disabling the write buffer will effectively disable 0WS operation, but just as a side effect.

Do you happen to know the register to enable/disable this? I read the 8900D datasheet but no register descriptions were included

maxtherabbit wrote on 2025-01-21, 02:08:

Do you happen to know the register to enable/disable this? I read the 8900D datasheet but no register descriptions were included

I'm sorry, I don't know the details here. I do know that later 8900 series utility disks included a program called "LOCKFIFO" that forces the FIFO to be disabled or enabled in certain modes. I remember I once reverse engineered part of it, and found out that the 8900B I had at that time doesn't have the register bits that are touched by LOCKFIFO. In retrospect, this is not surprising, because according to the performance figures, only the 8900CL and the 8900D seem to include that FIFO (which I called write buffer in my last post) at all.

noshutdown wrote on 2025-01-21, 01:42:

thanks a lot for the info, man. at least i know that its possible for cirrus, and i am considering buying a gainward cl-gd5429 with 2mb dram sockets but no 0wait jumper.
is there any ready-made programs that does this, or can i make one within a few lines of debug?

I'm sorry, that info was wrong. The wait state programming register is for local bus operation only. For ISA operation, the Cirrus Logic GD-542x series chips always output a 0WS signal, which can not be disabled in software, so a jumper is the only way to toggle between 0WS enabled and disabled.

The SIIG AVGA3 shown on https://www.vgamuseum.info/index.php/cpu/item … logic-cl-gd5429 has a jumper for 0WS operation: That's JP1, which is indeed located on the 0WS line from the Cirrus chip to the bus. Probably the board design is the Cirrus reference design, as I see the same board also sold under different brands like Prolink. Furthermore, I found pictures for a Diamond SpeedStar Pro card, that has a similar jumper, which is labelled 0WS. Furthermore, I found a picture of a "REVEAL VC500" aka "JA8228G/V2" card, also with a 0WS jumper labelled JP1.

On the other hand, I found a no-name "CL-GD5429-86QC", which is just the chip name (item 124412602119, you know what I mean), which does not have the required trace at all.

As a middle ground, the no-name card shown at https://ru.pc-history.com/video-card-cirrus-l … 16-bit-isa.html has the required trace, but the jumper is missing on that card.

If you post a (link to a) picture of that Gainward card, I can take a look at it. You can also try to look whether the ISA B8 contact is connected at all.

mkarcher wrote on 2025-01-21, 21:15:

If you post a (link to a) picture of that Gainward card, I can take a look at it. You can also try to look whether the ISA B8 contact is connected at all.

these are the pictures, see if you can find out what the traces and the missing jumper do.
as you can see, isa video cards with 2mb ram are not that common, only a few are known to exist: ati mach32/64, s3 928, tseng et4000/w32i and cirrus5434.

On that Gainward card, I can see a trace from ISA contact B8 to a position below the ROM chip, and then it continues on the front side of the card, which obviously is obscured by the ROM chip, and likely further obscured by the currently invisible logic chip beneath the ROM chip. Nevertheless, seeing a trace at ISA contact B8 at all is a good sign. Furthermore, I traced the connection from the CL-GD5429 chip, pin 51 (which is the 0WS pin in ISA mode) to pin 2 of JP1, and there is a trace from pin 3 of JP1 that also disappears below the ROM chip. So it is extremely likely that this card requires a connection between pins 2 and 3 of JP1 to make use of 0WS operation.