There seems to be two chip selects for stereo operation3s in DRO files? One is in the stream header (2/3 for first/second, where 0 is a delay instead for example) and one is documented for the bit 7 of the register before indexing into the iCodeMap table of up to 128?
How do those two settings combine to determine the chip to use (on Sound Blaster Pro and up that'd be 22[0/1] and 22[2/3], so it's controlling bit 2 of the I/O port?