VOGONS


First post, by xsaveopt

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Windows XP seems to be generating an interrupt on vector 0x3D by writing to the ICR in the LAPIC registers. It specifically sends the interrupt only to the current CPU, so it doesn't seem like this is intended for multi-core code. Is there any reason to do that over just INT 0x3D? To me it just seems like a very convoluted way to trigger an interrupt.

It also appears to be quite picky over the timing of delivery. Is there any official documentation on how quickly an interrupt must be delivered to the same core? I was under the impression that these interrupts were delivered asynchronously, but it seems that a delay of just 1000 instructions can make Windows XP bluescreen.

Reply 1 of 1, by superfury

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Well, INT is synchronous, while APIC isn't? APIC also sets ISR, while INT doesn't. Maybe software relies on the ISR registers in the APIC.
Also, APIC has interrupt priorities (3 in this case), while INT ignores it. There's the case of 'IRQL not less or equal' that comes into play too (TPR, PPR etc.).

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