Cyrix 5x86 Register Enhancements Revealed

Discussion about old PC hardware.

Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2011-12-09 @ 18:38

Cyrix 5x86 Register Enhancements Revealed



Did you ever wonder how much improvement those ‘special features’ of the Cyrix 5x86 processor gave? Well, in this study we will investigate the performance enhancing effects of each user configurable register bit settings of the Cyrix 5x86 central processing unit. 36 different benchmark tests were employed to determine the average probable performance enhancement for each feature independently. Many of these register settings, or features, are disabled from the factory by default as a means to increase compatibility with a broad range of motherboards. As the Cyrix 5x86 is a partially downscaled 6x86, many of the conclusions made herein will likely hold true for the Cyrix 6x86 processor.



EXECUTIVE SUMMARY

For the overall performance gain, enabling BTB (branch prediction) showed an 8.5% improvement, LSSER (load/store reordering) showed an 8% improvement, FP FAST (fast floating-point unit) showed a 6% improvement, and MEM_BYP (memory read bypassing) showed a 1.5% improvement. The other features tested were IORT, LINBRST, RSTK, BWRT, LOOP, DTE, WT and showed little to no improvement.



INTRODUCTION

This study adopts the ensuite of benchmarking software utilised in the Ultimate 486 Benchmark Comparison as a means to estimate the performance gain per Cyrix feature. These features were enabled/disabled using the IBM M9 Register Utility Version V1.22 (20 May 1996), however other popular programs of the time were the Peter N. Moss Register Bit Enabler Version C2 (12 May 1996) and ET586 Version 1.1 (28 November 1995) by Evergreen Technologies. The IBM utility was chosen because of its graphical user interface in DOS and the ease of enabling bits. Since Windows 98SE was selected for performing Windows-based benchmarks, a Cyrix NT driver was not needed; features were enabled in DOS prior to booting into Windows 98SE. If special Cyrix 5x86 features are desired in Windows NT and Windows 2000, Evergreen Technologies created ET586NT, which is an NT driver that runs as a device automatically at start-up. Below is a table containing a map of various Cyrix 5x86 register bits (CR0 is not included).

This table represents a snapshot of which Cyrix 5x86 features are set by the motherboard as default. The bolded entries are features which were later enabled using the IBM utility, that is, LSSER is to be changed to 0, LOOP_EN to 1, RSTK_EN to 1, BWRT to 1, and FP_FAST to 1. When enabled, the entirety of these settings constitute My Default Settings as noted on the chart in Appendix 2 (column A) and below. These settings are considered optimal/stable settings on the employed motherboard, a Biostar MB8433-UUD v3.0 with a Cyrix/IBM 5x86c-100HF running at 133 MHz (2 x 66 MHz) and 3.85 V. This voltage was selected as stable on this particular motherboard, CPU, and cooling environment, however other CPU/motherboard combinations may require a different core voltage for thermal/frequency stability. This stable voltage is typically in the 3.65 – 3.85 V range for 133 MHz operation.

Note that LSSER is optimal when it is set to 0, not 1. A feature is typically said to be enabled when it is set to 1, and disabled when it is set to 0 (except for LSSER, which is opposite). WT and IORT, when set to 0, are also theoretically the most optimal setting, however they exist mainly for reasons of cross-platform stability.



BIT ENABLING PROGRAMS

Since most motherboard manufacturers did not enable the special features of the Cyrix 5x86 in the BIOS, bit enabling software programs were generally required, however one manufacturer (PC Chips M919) allowed for two such features to be enabled in the BIOS (LINBRST and LSSER). While it is not well documented why more companies didn’t follow suit, is likely due to time constraints and the fact that the 486 was considered a low-end, low-priority item by mid-1996. Unfortunately, even the latest BIOS update for the Biostar MB8433 UUD, dated May 1996, does not include a user adjustable enabler for Cyrix features.

While the IBM utility uses a GUI as a means to enable the special features, the Peter Moss utility uses on/off flags to enable features, for example, to enable BTB_EN and RSTK_EN type, 5x86.exe /BTB_EN=on /RSTK_EN=on. The Evergreen utility is a little more cumbersome to use since you need to type in HEX values for an entire register (8 bits, or features, per register). For example, for the performance control register (PCR0), if you only want LOOP and RSTK enabled (and the other bits of this register disabled), you’d need to type, ET586.exe /PCR0=5, where 5 is hexadecimal digit. From the above chart, 00000101 in binary representation is equal to 5 in hexadecimal. Even more confusing is that the Windows NT/2000 driver from Evergreen Technologies requires its units to be in decimal. It just so happens that, in this case, 5 in hexadecimal is also 5 in decimal, though this is not always the case. Screenshots of the various bit enabler programs are shown in Appendix 1.

There exists a fourth bit enabling program called CyrixGo, or Free5x86, however it is very limited in which features it can enable.



TEST METHODOLOGY

The testing scheme used herein is such that all features known to be stable with the employed CPU/motherboard combination were enabled (referred to as DEFAULT SETTINGS in column A of Appendix 2, and My Test Settings in the Test Settings section of this report). Then a specific feature was turned off (i.e. LSSER = 1, or LOOP = 0, or RSTK = 0, etc.), and the decrease in benchmark scores were tabulated in an adjacent column (column B, LSSER). Before testing the next feature (column C, LOOP), the previous feature was re-enabled (LSSER set back to 0).

The reason for testing this way, that is, always having all of the most optimal features enabled except for the one being tested, was because it is unknown whether one feature will greatly alter the performance of another. It is assumed that a user would want all optimal features enabled, unless one needs to be disabled for reasons of instability. Such a case was discovered with LOOP, in which LOOP only seems to have a noticeable performance enhancing effect when BTB was enabled. LOOP enabled on its own did not improve performance.

The charts in Appendices 2 & 3 list the effects each feature had on the indicated benchmark program, while the charts in Appendices 4 & 5 normalise the results to that of the optimal/stable default settings (column A). This is done so that a relative change in performance can be established. Columns B thru I are the most common known stable features and column A contains results when all these features are enabled. Conversely, column J shows the results when B thru I are all disabled. Columns K*, L*, and M* are feature configurations which contain a performance boost from the chosen DEFAULT SETTINGS, however they are not likely to be long-term stable in Windows. IORT (column N), which controls the I/O recovery time, is generally a setting controlled by the BIOS, however the longest possible recovery time of 128 clock cycles was set to determine if this setting had any affect on performance.

While not a Cyrix-specific next generation feature, benchmark results were also tabulated for cases where the CPU’s L1 cache was placed into write-through mode, and with L1 cache entirely off (columns O and P, respectively). For these latter two features, it is important to remember that the DEFAULT SETTINGS of column A were still employed. For this to occur, for example as with setting the CPU into write-through mode, the CPU must still be set to write-back mode in the BIOS initially, then later changed to write-through mode in software, otherwise the next generation features (column A) did not have the same enhancing effects. That is to say, if you set your BIOS to L1 write-through mode, it was determined that later enabling the special features had less performance improvement than when setting L1 to write-through mode in software. To set the cache to write-through mode in software, it is first necessary to set LOCK NW = 0 then set CD = 0 and NW = 0.

Once all test results were normalised to DEFAULT SETTINGS, they were averaged for ALU- and FPU-specific tasks in terms of percent increases/decreases in performance. Some tests did not show any performance boost, however those too were equally averaged in. This method of performance characterisation has been termed Average probable boost as indicated on the bar graphs to follow. Since some tests showed a very large increase in performance while others showed little or no increase, the percent boost of the best test case is also included separately on the graphs and is termed Maximum observable boost. This difference is due to the fact that some CPU features enhance only specific instructions in the software code, while others do not. The performance boosts in the charts are ordered, or ranked, by their average probable boost. Both Windows and DOS results were grouped together; however Appendices 6 & 7 contain a DOS only section for those who are interested primarily in DOS performance.

Chart entries bolded in Appendices 2 & 3 indicate a change of greater than 2% from DEFAULT SETTINGS.



TEST SETTINGS

*Test System*

Biostar MB8433-UUD v3.0 Motherboard - UMC 8881F/8886BF, [BIOS: UUD960326S, 03/26/1996]
IBM 5x86C - 100HF at 133 MHz (Step 0, Rev 5), FSB = 66 MHz, CLKMUL = 2X, Vcore = 3.85 V, 1:1/2 FSB:PCI
64 MB Fast-page mode RAM (60 ns) [BIOS: 1WS/0WS]
512 KB Single-banked L2 SRAM Cache (15 ns), Write-back [BIOS: 3-2-2]

PCI Slot 1 = Adaptec 2940U2W PCI SCSI Controller w/Seagate ST373307LW Ultra320 Harddrive
PCI Slot 2 = 3Com 3c905C-TX-M, 10/100Base-TX (disabled in Windows)
PCI Slot 3 = Matrox Millennium G200 PCI Graphics Card, 16 MB SDRAM
ISA Slot 4 = Creative Labs AWE64 Gold, 28 MB RAM (CT4390)


*My Default Settings* - Cyrix 5x86 Register Bits

[PCR0=5h, CCR1=2h, CCR2=D6h, CCR3=1Ch, CCR4=38h, WBE (CD=0, NW=1)]

RSTK_EN = 1 Enables the return stack so that RET instructions will speculatively execute following a CALL. [1 is optimal]

BTB_EN = 0 Invokes the branch target buffer for instruction addresses, thereby inducing branch prediction. Not used. [1 is optimal]

LOOP_EN = 1 Enables the prefetch buffer loop for destination jumps still present in the prefetch buffer (prevents buffer flushing/reloading). [1 is optimal]

LSSER = 0 If set to 0, memory reads and writes to the load/store memory management unit can be reordered for optimum performance. [LSSER=0 is optimal]

WT1 = 1 Enables write-through in region 1 (640KB-1MB). Forces all writes to region 1 that hit the L1 cache to be sent to the external bus. [WT1=0 is optimal]

BWRT = 1 Enables the use of 16-byte burst write-back cycles. [1 is optimal]

LINBRST = 1 Enables a linear address sequence while performing burst cycles (as opposed to i486 "1+4" address sequencing). [1 is optimal]

FP_FAST = 1 Enables Fast FPU exception handling. [1 is optimal]

MEM_BYP = 1 Enables memory read bypassing so that data can be read from the write buffers prior to being written to external memory. [1 is optimal]

DTE_EN = 1 Enables the directory table entry cache. [1 is optimal]

IORT = 000 Specifies the minimum number of clock cycles between I/O accesses (I/O recovery time). [000 is optimal]

USE_WBAK = 1 Enables write-back L1 cache pins. [1 is optimal]
CD = 0, NW = 1 Enables write-back L1 cache. [01 is optimal]



For more information on how these features work and for what type of code they enhance, please refer to the Cyrix 5x86 BIOS Writers Guide, the Cyrix 5x86 Microprocessor Guide, the Cyrix 6x86 BIOS Writers Guide, the Cyrix 6x86 Data Book, the Peter Moss Utility’s documentation, and register for an introductory course in computer architecture.



RESULTS - ALU

From the graph shown above, it is clear that BTB had the largest impact for ALU-focused processes, with a 22% boost. BTB, or branch prediction, on a Cyrix 5x86 is generally not considered a stable setting in Windows except possibly with Stepping 1, Revision 3 CPUs. To get BTB working on Stepping 1, Revision 3 CPUs, it is necessary to disable LOOP, BWRT, and possibly RSTK. The CPU used in this study was Stepping 0, Revision 5. It was possible to run the noted Windows benchmark tests with LOOP, BWRT, and RSTK disabled, however the only way to boot into Windows was to first boot into DOS, then type win at the command console to enter Windows. BTB appears stable in DOS with both revisions of the CPU. To date, no other CPU revisions have been encountered. The Cyrix 5x86-80 and 5x86-100 came in Stepping 1, Revision 3 editions, whereas Stepping 0, Revision 5 CPUs came in 100, 120, and 133 MHz flavours.

It was recently discovered that Windows NT4/98SE/2000 all initially appear usable with a Stepping 0, Revision 5 CPU and all Cyrix features enabled (including BTB) except for LOOP, RSTK, BWRT, and DTE. Stability, however, had the tendency to decrease as the CPU was run longer (and began to heat up). This effect may be more of a consequence of running the CPU overclocked and above thermal spec for core voltage than with a broken feature. Some Cyrix features may be more frequency and/or thermal sensitive than others.

Referring to Appendix 6, we see that BTB did not have such a magnificent impact for DOS-only ALU tests; in DOS, performance boost dropped to only 5%. An interesting point to note from the DOS-only ALU chart is that LOOP yielded a performance gain only when used in combination with BTB, thereby bumping the results up another 1%. Also surprising was that RSTK seemed to have no effect on its own accord. Unfortunately, LOOP and BTB together were not very stable. They may only work together in 16-bit mode since Windows would not boot with this setting and 3Dbench, Doom, Pcpbench, and Quake wouldn’t run. It may be that BTB and LOOP work well together with Stepping 1, Revision 3 CPUs, however this configuration wasn’t been tested.

Next in line for performance was LSSER at 7.4%. It was previously thought that LSSER needed to be disabled (set to 1) for motherboards which contained in-use PCI slots, however the author has had LSSER enabled (set to 0) for years with 3 filled PCI slots and hasn’t had issues. From personal experience, the Biostar MB8433-UUD and PC Chips M919 both functioned with LSSER enabled.

Surprisingly, setting the L1 cache scheme to write-through mode instead of write-back only indicated a 4% improvement for ALU performance, though some tests showed as much as a 12% improvement. It should be noted that all other enhancements were still enabled. If write-back L1 cache is disabled in the BIOS instead of through software, it may not be possible to fully enable other Cyrix special features (although they may appear to be enabled).

LINBRST, which is noted in the Cyrix literature as improving performance, only helped by an average of 0.5%. Your motherboard’s chipset must support linear burst write cycles to enable this feature, otherwise your system will crash upon enabling it. While both the Biostar and M919 support LINBRST, there seemed to be no real performance boost, unless perhaps this feature cannot be disabled in software once the BIOS has enabled it. If this is the case, the only way to test for it would be to use a comparable motherboard which does not support this LINBRST, such as the Shuttle HOT-433. Only CPUMark32 in Windows caught the 4% improvement with LINBRST.

MEM BYP had the same ALU fate as LINBRST, with only a 0.5% improvement, however some tests weighed it in at 3.3%. FP FAST also didn’t do much for ALU operations. Surprising is that IORT, which was set to 128 clock cycle delays, didn’t seem to drop the performance much. It may be that the BIOS took over this setting without the possibility for intervention, however setting IORT to 128 clock cycles did drop the frame rate in DOOM by 5 fps.

WT, when enabled, sets only the memory region from 640 KB – 1000 KB into write-through mode (as opposed to write-back mode). When set to 0, you get write-back mode in this small region of memory, though doing so causes Quake not to run, and will yield an extra 2 fps in Doom. DTE and BWRT also had little to no effect on performance.

To summarise this section, if you can get BTB working, use it with a smile. LSSER is next in line for performance boost. Don’t be too bummed if you cannot get the other features working, though if you can, adding up all the effects of the weak performers adds another 1% of boost on top of LSSER. If all stable/optimal enhancements are enabled, you should see a 13.5% ALU performance boost (B – I), though some applications may see up to a 50% boost. If you can get BTB working, you may see another 8.5% of ALU boost. From the Ultimate 486 Benchmark Comparison, the combined total boost of these Cyrix 5x86 register features weighs the ALU of a Cyrix 5x86-133 in at about the level of an AMD X5-160, or a Pentium 100 with pipeline burst cache enabled. Not too shabby for a low-cost, low-power 486.



RESULTS - FPU

The floating-point units (FPU), or co-processors, of microprocessors are used extensively in high-performance games, simulation software, mp3 conversion, modeling, etc, so depending on your intended use of the processor, these results may be more (or less) important than the ALU results. Starting with BTB, we see that, on average, enabling this feature decreased ALU performance, but only in Windows. In DOS, it enhanced performance by about 2%. This performance drop wasn’t an isolated case, since WinTune98, Sandra99, and PassMark all indicated a drop in performance.

The clear leader for FPU performance enhancement was FP FAST, which boosted the average FPU test results by 18%. Next in line was LSSER with 11.4%. MEM BYP helped by as much as 1%, while all other features had a relatively low average probable boost. It may be naive to entirely dismiss the other features since some tests indicated significant improvement. MEM BYP, BWRT, and LINBRST all had about a 5% improvement for the best case test. Even BTB, whose average is negative, improved performance by 13% in some tests.

The entire ensemble of stable/optimal features improved FPU performance by about 22%, and from the Ultimate 486 Benchmark Comparison, a Cyrix 5x86-133 rates in at about a Pentium 90. Even an AMD X5 overclocked to 200 MHz was about 4 Pentium ratings (PR points) below the Cyrix 5x86-133 in FPU-related tasks.



RESULTS - OVERALL

The overall performance graph encompasses a much larger number of tests than either the ALU- or FPU-specific graphs so the overall results are far more encompassing. The above graph can speak largely for itself. In line with the conclusions made in the ALU and FPU sections, BTB, LSSER, FP FAST, and perhaps MEM BYP are the most important of all the Cyrix 5x86’s special features. The Symantec (Norton) Sysinfo benchmark program really seemed to think that MEM BYP hot stuff; it boosted the results of this test by 18%, however the average probable boost was a mere 1.4%

Considering that LSSER had a large impact on both ALU and FPU operations, it may be considered the most important Cyrix feature to enable. While BTB looks like a big contributor overall, it had less than half the performance of LSSER for DOS-only activities (not to mention its poor FPU performance). Rated second is a toss-up between BTB and FP FAST; it is hard to look past the whopping 18% improvement offered by FP FAST. In fourth place is MEM BYP, followed perhaps by LINBRST and BWRT.

The write-back caching scheme of the Cyrix 5x86 is charted mainly out of curiosity and is not a feature specific to Cyrix 5x86 processors. Both AMD and Intel employed write-back caching in their later 486 CPU revisions.

Looking now at the raw DOS gaming scores, LSSER and FP FAST showed the most improvement in Quake, gaining about 1.3 fps each, while BTB only improved Quake by 0.3 fps. With all stable Cyrix features (B – I) considered, we see about a 2.6 fps gain in Quake and about 2 fps gain in Doom. For 3Dbench, all stable Cyrix features (B – I) improved the score by 3%, whereas BTB alone improved the score by 4%.

A list of register settings I use for a variety of other CPUs can be found here, viewtopic.php?f=46&t=45756
Attachments
Cyrix5x86_Utilities.zip
Evergreen 586 Utility, Peter Moss 5x86 Utility, & IBM M9 Utility. CyrixGo & 6x86CTL are for use with Cyrix MediaGX.
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Cyrix-5x86_Register_Enhancements_Revealed.pdf
This is the full version of the report which contains this text, plus raw/normalised data, seperate DOS/Windows graphs, a bit enabler map, and screenshots.
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Last edited by feipoa on 2018-4-19 @ 21:31, edited 9 times in total.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2011-12-09 @ 18:41

Some charts from the PDF.
Attachments
IBM_5x86_Utility.jpg
IBM_5x86_Utility.jpg (135.19 KiB) Viewed 13801 times
Cyrix_Registers_ALU.png
Cyrix_Registers_ALU.png (12.2 KiB) Viewed 13801 times
Cyrix_Registers_FPU.png
Cyrix_Registers_FPU.png (12.1 KiB) Viewed 13801 times
Cyrix_Registers_Overall.png
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Bit enabler map
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby elianda » 2011-12-10 @ 09:18

Wow, thats some real 'in detail' information. Good work!

I still wonder, why Windows does not work with certain setting while DOS works. I would expect it has something to do with Protected Mode Task switching.
So the unstable setting regarding to Windows is stable in usual DOS apps like DOS4GW / PMODE/W / QEMM / DESQVIEW etc. ?
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2011-12-10 @ 11:04

I was wondering the same thing, but unfortunately I am not familiar enough with microprocessor architecture to offer an insightful hypothesis.

My main interest with register enhancement stability now is to get BTB working in Windows on Stepping 0, Revision 5 CPUs. Since these are the later produced CPUs (over Stepping 1, Revision 3 CPUs), it would just seem most natural for BTB to function properly.

I've begun some initial tests to determine which combination of register settings cause BTB to be unstable in Windows, and so far on my IBM 5x86c-133 (2x66 MHz), I can get BTB working in Windows 2000 with LSSER, FP FAST, LINBRST, and MEM BYP enabled while RSTK, LOOP, BWRT, and DET are disabled. It has been up for 25 minutes now just doing some disk defragmenting and mp3 playback; it hasn't crashed.

The conclusions made in other literature stating BTB it is unstable may be due to the fact that the testers didn't figure other enabled features would conflict when BTB was enabled. Luckily, RSTK, LOOP, BWRT, and DET do not seem to impact performance much, so I am content to disable them. The only one scenerio I did not test for from this unveiling is if RSTK, when enabled, will assist when BTB is enabled, kinda like how LOOP only has an impact when BTB is enabled.

Your comment prompted me to add this line to the report,

It was recently discovered that Windows NT4/98SE/2000 all initially appeared stable with a Stepping 0, Revision 5 CPU and all Cyrix features enabled (including BTB) except for LOOP, RSTK, BWRT, and DTE. Stability, however, had the tendency to decrease as the CPU was run longer (and began to heat up). This effect may be more of a consequence of running the CPU overclocked and above thermal spec for core voltage than with a broken feature. Some Cyrix features may be more frequency and/or thermal sensitive than others.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2011-12-11 @ 05:25

To add to the comments made in the previous post, I noticed that a branded Cyrix 5x86-133GP/4x will also work with branch prediction (BTB) on, but once the CPU starts to warm up, the system will crash. Voltage modification may help somewhat to find a sweet spot.

It may not necessarily be that only Stepping 1, Revision 3 CPUs are stable with BTB as previously thought, it just may be that BTB only works long-term at 100 MHz or less. Since Stepping 1, Revision 3 CPUs only came in 80/100 MHz flavours, perhaps people assumed that this revision was the only stable candidate for branch prediction. It may very well be that a Stepping 0, Revision 5 CPU running at 100 MHz will be just as stable with BTB. Has anyone tried this?

Running actual tests would clear up this speculation.

I generally use Win NT/2000 to establish stability. The problem is that if you put in unstable settings to the 5x86 device driver, the system may not boot, in which case, if you have a dual-boot machine, boot into the other operating system and delete ET586NT.SYS from \WINNT\System32\Drivers\. Then reboot and change the driver's setting, and place the ET586NT.SYS file back into ...\Drivers upon boot-up. Now reboot. If you are running NTFS on a uni-boot system, the way to get back into Windows to change the 5x86 device driver settings is to put in an AMD CPU, boot, change the settings, put the Cyrix back in, and reboot.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby elianda » 2011-12-11 @ 12:13

Driver resets/deletes are always quite time consuming, maybe try this approach:
Install QEMM with Quickboot feature enabled in the DOS boot branch. Set the CPU features there and then warmboot by ctrl-alt-del or warmboot.com.
Due to Quickboot you will not go through the BIOS again which would reset the CPU feature setting. Your boot Menu will appear and you can boot with set CPU features to NT or 2K.
If there is no driver in NT or 2K that changes the Cyrix CPU feature setting, you can use a NT system that is always identical.
If it crashes just boot back to DOS and change CPU feature settings.

The QEMM DOS booter can be put on a Disk also, just make sure Quickboot targets C as boot drive.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2011-12-11 @ 16:40

I did not think you could use QEMM with NTFS partitions in a Windows NT 4.0 only system.

My main Cyrix system is a 4 GB NTFS partition running Windows NT 4.0. It also has a 140 GB NTFS HTTP server partition (Ultra320 SCSI). Could you list step-by-step how to install your scheme for this environment?

On the other hand, my experimental system at 2x66 MHz has Win98SE/NT4.0/W2K on 2 GB FAT partitions. I can see how to install QEMM here, but it looses its value as I can easily boot into any other Windows and fix the problematic Cyrix driver.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2011-12-24 @ 15:41

Has anyone else had success with branch prediction using stepping 0, revision 5 Cyrix CPUs?

It seems quite usable with the right combination of features turned on/off, even at 133 MHz.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2012-2-15 @ 08:58

I've had pretty good luck running an IBM 5x86c-100HF (stepping 0, rev. 5) at 2 x 66 MHz (3.7 V) with branch prediction enabled within Windows 98SE. I have found these settings to be pretty stable,

Enabled: BTB_EN (=1), LSSER (=0), FP_FAST (=1), LINBRST (=1), MEM_BYPE (=1)
Disabled: LOOP_EN (=0), RSTK_EN (=0), DET_E (=0), BWRT (=0)

Disabling LOOP and RSTK is essential. Disabling DET and BWRT might just help with high frequency (133 MHz) stability.

LINBRST may only be enablable on '96 and newer UMC chipsets, particularly FX_ (southbridge) and EY_ (northbridge) ones.

On another note, the the comparative results contained herein may not be entirely complete for Linear Burst Mode (LINBRST). If the 5x86 is anything like the 6x86 (MII), it may not be possible to fully disable LINBRST once it has been enabled. The MB-8433UUD used in this study natively enabled LINBRST, so the 5x86 results which indicate a mere 0.5% improvement for LINBRST may not tell the whole story. I would need to test the 5x86 on a UMC-chipsetted motherboard which does not natively enabled LINBRST, such as a HOT-433. According to the Cyrix MII data sheet, L1 cache must be disabled, LINBRST enabled, then L1 cached enabled, in that order.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby gwb » 2012-2-17 @ 21:36

This such a beautifully crafted thread. Bookmarked for later reading tonight!
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2012-2-18 @ 03:19

There's an all inclusive PDF in here which prints really well. I find it makes for a good bedtime story (while in bed). This document accompanies the Ultimate 486 Benchmark Comparison quite nicely. I may just read it to my first born.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby dirkmirk » 2012-2-18 @ 05:50

Those 2 guides are awesome, you really went out of your way but I very much appreciate it!

I've been fiddling around with my 5x86-120 and I get the feeling the POD83 is a better CPU for first person shooters, even with the cyrix enhancements, I'll need to build another PCI 486 system as I dont like swapping cards in my fragile system.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2012-2-18 @ 07:51

That result seems agreeable with what I uncovered, particularly with Quake, and to a lesser extent, with Doom.

What motherboard, hardware, and BIOS settings are you using? All of which Cyrix enhancements did you enable? Some motherboards have issues with enabling the POD's L1 cache.

Have you tried running your Cyrix 5x86 at 2x60 MHz instead of 3x40 MHz?

I just saw a Cyrix 5x86-120 sell in a mass CPU gold recovery eBay auction. I pleaded with the seller, but it could not be saved (he wouldn't pull it from the sold auction lot). Thankfully it was not the rare 120/4x variety. He seemed to think that he'd get more in, but I doubt it.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby sliderider » 2012-12-14 @ 19:28

Where can you download the programs that allow you to activate the deactivated features and which one allows the most options to be turned on?
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2012-12-15 @ 00:38

sliderider wrote:Where can you download the programs that allow you to activate the deactivated features and which one allows the most options to be turned on?

After reading through the documentation from the accompanying the utilities, it seems OK attach them. I have included the IBM, Evergreen, Peter Moss, and CyrixGo utilities in a zip file with the original posting.

I generally use the IBM utility if I want a quick means via a GUI to enable/disable a feature, but for automatic loading in DOS and Windows, I use the Evergreen utility. For the Evergreen utility, you need to do a lot of binary to HEX (in DOS) and binary to DEC (for WinNT) conversion. No conversion is needed for Peter Moss or IBM. The CyrixGo utility was the most limited in terms of features. I think IBM and Evergreen are on par and Peter Moss may have been missing a few unimportant features.

Note: Some of my comments were added to the Evergreen_Utility.doc file. Particularly, nowhere did the readme files mention that the WinNT/ W2K driver values need to be input in DEC, whereas they need to be input in HEX for the DOS driver. I noted this twice in the doc file.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2012-12-22 @ 23:37

sliderider wrote:
feipoa wrote:
sliderider wrote:Do you happen to know if there is a difference between a 5x86 GP and a 5x86 QP besides the packaging? Also, what motherboard multiplier is 4x mapped to?

I'm pretty sure G and Q are just packaging. The QP's I have seem to work the same as the GP's.

For 4x-capable Cyrix 5x86 chips,
2x on motherboard = 4x on the CPU
3x on motherboard = 3x on the CPU

For 3x-capable Cyrix 5x86 chips,
2x on motherboard = 2x on the CPU
3x on motherboard = 3x on the CPU

When can you test this baby out?


I just tested it! I put it in one of my M919's. I set the frequency jumpers down to 25mhz, though, because I didn't know what speed it would boot up at and didn't want to burn it out before I even had a chance to use it. At 25mhz frequency it reports 100mhz at bootup. The system I used doesn't have a hard drive installed, though, so I couldn't get past the initial bootup screen.

Edit: I found a diagram at stason for these boards and figured out how to put into 3x. I set it to 3x and frequency to 40mhz and it now boots at 120mhz.

So it looks like it maps 4x automatically to 2x so there is no chance at all of running 50, 60 or 66mhz bus with these. And since they don't overclock well, it looks like 33 x 4 or 40 x 3 is as far as you can go with these.

Now to find a suitable hard drive that isn't only good for scrap metal.

I only have v3.4 of the m919. There is a high res photo of v3.4 in the Ultimate 486 Benchmark Comparison link. Does the jumper layout look the same? I would be very surprised if v3.2 could not set the jumper for 3x. You probably just need to know the jumper to remove/set. 3.2 Volts is way too little for the chip to be stable. You'll want to run it at 3.7 V for 133 MHz, or you may get lucky with 3.45 V and 120 MHz.

The M919 doesn't do a 66 MHz FSB well, but 60 MHz seems OK. As we discussed earlier, you can still run it at 2x60, but you need to start it out on 4x33, or whatever, then write to the Cyrix register (via software) for 2x operation, then switch the FSB to 60 MHz (jumper).
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby sliderider » 2012-12-22 @ 23:42

feipoa wrote:
sliderider wrote:
feipoa wrote:
sliderider wrote:Do you happen to know if there is a difference between a 5x86 GP and a 5x86 QP besides the packaging? Also, what motherboard multiplier is 4x mapped to?

I'm pretty sure G and Q are just packaging. The QP's I have seem to work the same as the GP's.

For 4x-capable Cyrix 5x86 chips,
2x on motherboard = 4x on the CPU
3x on motherboard = 3x on the CPU

For 3x-capable Cyrix 5x86 chips,
2x on motherboard = 2x on the CPU
3x on motherboard = 3x on the CPU

When can you test this baby out?


I just tested it! I put it in one of my M919's. I set the frequency jumpers down to 25mhz, though, because I didn't know what speed it would boot up at and didn't want to burn it out before I even had a chance to use it. At 25mhz frequency it reports 100mhz at bootup. The system I used doesn't have a hard drive installed, though, so I couldn't get past the initial bootup screen.

Edit: I found a diagram at stason for these boards and figured out how to put into 3x. I set it to 3x and frequency to 40mhz and it now boots at 120mhz.

So it looks like it maps 4x automatically to 2x so there is no chance at all of running 50, 60 or 66mhz bus with these. And since they don't overclock well, it looks like 33 x 4 or 40 x 3 is as far as you can go with these.

Now to find a suitable hard drive that isn't only good for scrap metal.

I only have v3.4 of the m919. There is a high res photo of v3.4 in the Ultimate 486 Benchmark Comparison link. Does the jumper layout look the same? I would be very surprised if v3.2 could not set the jumper for 3x. You probably just need to know the jumper to remove/set. 3.2 Volts is way too little for the chip to be stable. You'll want to run it at 3.7 V for 133 MHz, or you may get lucky with 3.45 V and 120 MHz.

The M919 doesn't do a 66 MHz FSB well, but 60 MHz seems OK. As we discussed earlier, you can still run it at 2x60, but you need to start it out on 4x33, or whatever, then write to the Cyrix register (via software) for 2x operation, then switch the FSB to 60 MHz (jumper).


Chrome is giving me a malware warning. Somewhere on that page someone is linking to a photohosting site that distributes malware.

Anyway the 3.2 looks similar only it is green and has 2 72 pin and 4 30 pin slots and has the fake cache chips soldered on. I managed to pick up one with the cache module in it. The last cache module I saw on ebay sold for $100 by itself and the board I found that had it in it was a lot less than that so I grabbed it.
Last edited by sliderider on 2012-12-22 @ 23:50, edited 2 times in total.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2012-12-22 @ 23:46

sliderider wrote:Chrome is giving me a malware warning. Somewhere on that page someone is linking to a photohosting site that distributes malware.

Are you refering to the Ultimate 486 Benchmark Comparison thread with the link to the Elpina M919 photo? Chrome loads it fine for me.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby sliderider » 2012-12-22 @ 23:48

feipoa wrote:
sliderider wrote:Chrome is giving me a malware warning. Somewhere on that page someone is linking to a photohosting site that distributes malware.

Are you refering to the Ultimate 486 Benchmark Comparison thread with the link to the Elpina M919 photo? Chrome loads it fine for me.


Yeah, it did it three times then I finally clicked on take me there anyway so I guess now it won't do it anymore. I was editing the post above when you entered yours so look up for new info.

And it seems like too much trouble to have to manually change the multilpier and frequency every time it's booted up. I''ll just try my luck at 40 x 3 once it's closed up.
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Re: Cyrix 5x86 Register Enhancements Revealed

Postby feipoa » 2012-12-23 @ 01:16

That is why you wire the proper FSB combination to the turbo button. Taking the FSB settings on the MB-8433UUD as an example,

40 MHz
JP15, JP16, JP17
open, closed, closed

60 MHz
JP15, JP16, JP17
open, closed, open

It is only JP17 that needs to be flipped, so a single pole, single throw switch is all you need. You can use the two leads on the turbo button's single pole, double throw switch to open and close JP17.

So you would boot up at 3x40 (120 MHz), use the Evergreen Cyrix utility to change the multiplier from 3x to 2x (you can set the Evergreen utility to do this at boot automatically), then push the turbo switch to run at 2x60 (120 MHz). This is the easiest way to do it. Alternately, you can use a transistor as a switch or a relay to have the FSB jumper switch automatically, either after some single at boot, or on a timer.

I checked my M919 manual, it is also only a single jumper change between 40 and 60 Mhz. It is a matter of moving the turbo button lead onto the FSB jumper, JP3C (M919), or JP17 (MB8433).
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