First post, by superfury
What happens in Supervisor mode when the kernel tries to write to a read-only user page(lower 3 bits of the PDE and PTE are set to 5)? Does the write access succeed(happens according to test386.asm's tables and test routines)? So the CPL(which is zeroed) has direct effect on this(besides the tables mentioned in the CPU documentation clearly resulting in "User R", thus meaning a read-only user privilege page)?
The 80386 programmer's reference manual does state:
6.4.1.2 Type Checking
At the level of page addressing, two types are defined:
Read-only access (R/W=0)
Read/write access (R/W=1)
When the processor is executing at supervisor level, all pages are both readable and writable. When the processor is executing at user level, only pages that belong to user level and are marked for read/write access are writable; pages that belong to supervisor level are neither readable nor writable from user level.
So CPL0 ignores the R/W bits in the PDE and PTE? Also, the TLB is written as if the PDE and PTE have combined write access(required for the kernel to even address said data), forcing it to 1 instead of the PDE/PTE combined write rights(1 for writable, 0 for read-only).
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