First post, by superfury
What bits in the registers enable the 8-bit attribute (combining 2 4-bit pixels into 8-bit when rendering)?
I know of the 8-bit (bit 0x40) in the Attribute Mode Control register and the Attribute Misc regiser bits 4-5 on the ET4000(8-bit when 1, 16-bit when 3, 4-bit otherwise or Attribute Mode Control register-dependent).
Does the Sequencer Mode Control register bit 3 have effect on this? I remember reading something about that in the past, but can't find it atm(linear graphics mode according to ET4000 manual)?
Perhaps the GDC indexed register 5 bit 6?
Those three bits are documented as follows:
Sequencer memory mode register bit 3:
Bit 3, when set to a 1, will enable Chain 4 (linear graphics) mode, where all four memories are chained linearly into a byte-ori […]
Bit 3, when set to a 1, will enable Chain 4 (linear graphics) mode, where all four
memories are chained linearly into a byte-oriented memory array whereby each
byte will provide the eight bits (256-color) for each pixel. When set to 0, the processor will access data sequentially in the bit plane. When set to 1, causes the
two low-order bits of the address (A1 and AO) to select the plane that is accessed
GDC indexed register 5 bit 6:
Bit 6, when set to 0, permits the loading of the ATC's shift registers to be controlled by bit 5. When set to one, the registers are loaded to support the 256-color
Attribute mode control register bit 6:
Bit 6, when set to 1, halves the rate of pixel output to the screen, such that only
4, instead of the usual 8, pixels are output in a character clock time. This is normally used only for the 320x200 256-color graphics mode. For all other 256-color
modes, this bit should be set to 0
So, apparently, for the ET3000/ET4000, the Attribute Mode Control register halves pixel output, but doesn't affect the 8-bit color rendering in any other way?
So the only other bits that affect this are somehow GDC indexed register 5 bit 6 and Sequencer memory mode register bit 3?
I already found out that Windows NT 3.1 seems to clear the memory mode register bit 3 when not rendering stuff on the display?
So that would mean that the GDC indexed register 5 bit 6 is the only bit that affects the 8-bit color generation by the attribute controller(combining two 4-bit pixels to two 8-bit pixels)?
Edit: So, that would mean that the Sequencer memory mode register bit 3 still affects it's different meaning for the memory map addressed by the CPU, the GDC mode control register controls 8-bit operations by the Sequencer and Attribute controller, while the Attribute mode control only applies to pixel doubling(effectively an alternative to dot clock rate)?