I've tried to make an estimation on how all VGA and SVGA clocks interoperate(mostly how UniPCemu operates as well, with exception to the dot clock divided by 2 and DAC operation clocking(based on attribute stalling only, the noted "dot clock" has a seperate source based on the MCLK(may be divided by 2) of the Sequencer stage provided by the CRTC timing algorithms)):

Can anyone confirm this behaviour?

The divide dot clock by 2 is a strange one. In order to work properly, the DAC needs to depend on the Attribute controller(and 256-color mode setting by the Attribute controller) in order to properly stall and not send any new pixels on the screen for the duration of the attribute controller latching? The dot clock divide by 2 then needs to apply to the clock sent to the DAC as well(for the DAC to double the pixels only after the attribute controller has latched the second pixel)?

Managed to get the timings in the document working.

Although I did need to halve/quarter the DAC output pixels multiplier at the end for 320x200 32k/64k two pixel latching modes by using the MCLK/2 and MCLK/4 divider in the Sequencer register 07h when the DAC is operating in 15/16-bit mode, as all other registers apparently can't be properly used for detecting this case. Otherwise, the display would become around 350 pixels wide instead of the proper 800 pixels(VGA display resolution afaik is 800x600).

Having implemented those, now all color modes tested by WhatVGA (including the new 24-bit modes on the new DAC) work properly. All that's left is to check whether Windows 95 is still running properly with it.

Edit: Still running! 😁 Now all color modes should work without issues! 😁

Hmmm.. Slightly related. Can Disney's Villain's revenge for Windows 95 support the 24-bit true color mode? The manual and software says it needs 16-bit or 32-bit modes?

Edit: It runs in 16-bit color depth. It does give a "Bad stop code" error before displaying the sound test menu, though?

Eventually managed to make it a bit more simple to render without dividing the output for the 8-bit modes and up for most of the time.

Now, all modes render to the screen with a 1:1 ratio of rendered pixels. The only exception is the 24-bit color mode (active display pixels rendered at 3:1 ratio, with both active display and overscan being rendered at a 3:1 ratio).
Then, there's some slight doubling/quadrupling being applied during active display when the DAC isn't in 16/24-bit mode on the Tseng chips (ET3000/ET4000):
MCLK/2 and MCLK/4 (TS register 07) double and quadruple(respectively) the rendered pixels when in 8-bit mode without linear mode.
MCLK/2 and MCLK/4 (TS register 07) double and quadruple(respectively) the rendered pixels when the DAC latches 2 bytes per pixel and both 8-bit mode and linear mode are set.
Those are mainly for fixing the 320 pixel modes in both 8-bit VGA and 16-bit modes(modes 13h, 0313h and 0413h). Otherwise, they only render 320 pixels to the active display due to missing dot clock divide by 2 not being set.