I know that the RAMDAC I'm emulating can latch multiple pixels(8-bit) and combine them into a single pixel(16, 24 or 32-bit) color.

What happens when those clocks are received? What happens to the display output while the pixels are only partly latched? Is the display CRT not advancing it's horizontal location while this is happening(e.g. only the first byte of a 16-bit pixel or first or second byte of a 24-bit pixel is received on the current clock)? That's what UniPCemu is currently doing with it's new emulation(only rendering a single finished pixel color once, with 24-bit pixels being triple sized on the raster).

Anyone knows how this works? How does PCLK ticking seperate 8-bit pixels (which triggers the 2 or 3 latching stages) affect the output with 16-bit and 24-bit pixels (supplying 8-bit pixels for each PCLK)?

Documentation of the chips tell me that it's latching on every PCLK, but nothing is said about what happens to the DAC outputs while this is happening? Is the DAC advancing the beam while it's still latching and not gotten a complete pixel color? Does it advance multiple pixels with the same color when it's gotten such a multipixel color (not advancing the beam in the meantime)? Or (which I assume) does it keep sending the previous pixel until a new pixel is completed(for the 2(24-bit) or 1(8-bit) PCLK clocks it's gathering/latching a color to send)?