How does the i450gx chipset handle all things not directly mentioned in it's documentation?
Like SMRAM initialization(it only mentions handling when SMIACT# is active, so when it's in SMM), mouse/BIOS flash(mainly write protection for the flash chips)/keyboard/RTC, PCI interrupt routing(IRQA-IRQD), IRQ0/1 routing, SMI control, SMI triggering reasons, SMI reason reporting, IDE support(what's the use if a motherboard doesn't have IDE ports?).

Although I currently also have a PIIX3 IDE device in it's configuration space and header type forced to 0x80 (it's otherwise still the PIIX3 IDE controller, with no other differences in it's implementation).

Wikipedia (https://en.wikipedia.org/wiki/List_of_Intel_chipsets) only lists a EISA PCI bridge and a SIO.A chip (which would only be a plain I/O APIC only as far as I can understand from it's documentation on the northbridge).

I do see various options for enabling SMI in the documentation of the 450gx, but nothing about generating them?
Edit: Or is the SIO.A chip actually doing all of those? I'm kind of confused about that chip. Is it just the I/O APIC chip, or does it include all other SIO functionality as well (looking at the document "82378ZB SYSTEM I/O (SIO) AND
82379AB SYSTEM I/O APIC (SIO.A)")?

Edit: OK. Just read the entire "82378ZB SYSTEM I/O (SIO) AND 82379AB SYSTEM I/O APIC (SIO.A)" datasheet (although roughly skimmed through the registers in the PCI configuration space only). It looks like it's actually the equivalent of the PIIX3 PCI configuration space, but more simple (as most of the PIIX configuration is already done by the northbridge, which in this case is the 450gx PB/MC chips).
So I'll just need to implement that extra PCI configuration space to make the 450gx chipset complete.

I do see something very interesting (wrt the APIC being used) in there, though: register 70h, bit 0(INTRC). It's behaving like the IMCR in the newer machines? I almost wonder if the i430fx/i440fx also have such a bit (which would explain it's missing of said register).... Hmmm...
Edit: It doesn't seem to have any on the PIIX and PIIX3 chipsets? But it does support all other APIC hardware?