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PIIX/PIIX3 PIRQ mapping?

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First post, by superfury

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The PIIX/PIIX3 has the PIRQ mapping registers in PCI space registers 40h-43h.

Does anyone know how these PIRQA-PIRQD map to the INT lines on the devices, based on the device number and the PIRQ number (A=0, B=1, C=2, D=3 in said calculation)?
On the devices INTA=0, INTB=1, INTC=2, INTD=3.

Is there a simple formula to use in this case?
Like INTnr=(devicenr+PIRQnumber) MOD 3? Of course that's for any given PIRQ pin that's being calculated.

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Reply 1 of 2, by superfury

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Hmmm...
https://tldp.org/HOWTO/Plug-and-Play-HOWTO-7.html

One method of doing this would be to have wire LNKA share interrupts 1A, 2B, 3C, 4D, 5A, 6B, 7C. This is done by physically connecting wire W to wires 1A, 2B, etc. Likewise wire LNKB could be connected to wires 1B, 2C, 3D, 4A, 5B, 6C, 7D, etc. Then on startup, the BIOS maps the LNKB, LNKA, LNKC, LNKD to IRQs. After that, it writes the IRQ that each device uses into a hardware configuration register in each device. From then on, any program interrogating this register can find out what IRQ the device uses. Note that just writing the IRQ in a register on a PCI card doesn't in any way set the IRQ for that device.

Is that how it's mapped on an actual PCI system (i430fx/i440fx/i450gx PIIX/PIIX3)?

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Reply 2 of 2, by superfury

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OK. With the latest changes and the BIOS configured to route the first (which is what I assume PIRQA) to IRQ 10, I see the PC Doctor 2004 app reporting that the card is connected to IRQ '10' when asking it to display PCI information?

I have the first IRQ lane set to IRQ 10 in the PnP settings. All others are disabled atm. Although effectively, the only free IRQ numbers in the ISA range on the PCI chipsets are 5(since there's no 3rd parallel port) and 10. Of course, the IO APIC lines 16-20 are mapped to the PCI A-D lines always (not configurable).

Edit: OK. The first IRQ lane(INTA) is indeed mapped to IRQ10. And the others are properly mapped to IRQ5, as I've specified in the settings of the i440fx BIOS.
So the mapping is working properly for the PCI lanes it seems (at least for the first IRQ)?

It seems to think that PIRQA is connected to device number 1 though? So the first slot is at device 1, while the remainder works the same?
So the PIRQ lines are to be shifted up by one line to work properly on the root bus (device 0 is on PIRQD/PIRQ3)?

Edit: Just added support for the Command Register's Interrupt Disable bit and the reporting of the device's INTx pin on the Interrupt Status register bit 3.
Edit: OK. When the i440fx is left in it's default configuration, it assigns it to IRQ11? But IRQ11 is already used for the ET4000/W32 and other VGA controllers?

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