bakemono wrote on 2023-01-01, 11:26:

Nothing to do with emulation, but since there are a lot of these x86 minutiae topics in this forum here is my question. According to https://wiki.osdev.org/Paging a PDT entry configured as a single 4MB page (PS=1) has provision for address bits 32-39. What CPUs does this work on? And is it required for PAE to be enabled?

The goal would be to access above 4GB from a 32-bit driver. There is already some commercial software that claims to do this (like this one mentioned in another thread https://www.romexsoftware.com/en-us/primo-cac … e/overview.html ) but I don't know if PAE is required.

CPUID (late 486 or Pentium at least) tells if it's available and used. Those upper address bits(32-39, upper bit determined by something called "MAXPHYADDR") are always enabled when PAE is disabled and PSE in CR4 is set. Those bits in the PDE/PTE entries can't be toggled off for legacy if supported on the CPU. Support for it is indicated by EDX bit 17 of CPUID leaf 01h.
MAXPHYADDR is 36 bits, unless leaf 80000008h EAX bits 7:0 is available.
https://patchwork.kernel.org/project/kvm/patc … ost@redhat.com/

So PSE and PAE are pretty well separate things then, and using PSE alone to get extra address bits seems like it could be feasible. If I read CR4 from my driver it shows 0x00000691, so PSE (bit 4) is already enabled.

I'm thinking my next experiment will be to map the physical memory containing the current PDT (based on the address from CR3) and try to read out the data...

bakemono wrote on 2023-01-02, 20:55:

So PSE and PAE are pretty well separate things then, and using PSE alone to get extra address bits seems like it could be feasible. If I read CR4 from my driver it shows 0x00000691, so PSE (bit 4) is already enabled.

I'm thinking my next experiment will be to map the physical memory containing the current PDT (based on the address from CR3) and try to read out the data...

Do remember to check if the bit in EDX bit 17 of CPUID leaf 01h is set (as well as the bit for PSE of course). Otherwise you'll end up setting bits that are ignored by the CPU Paging Unit that make it use the wrong memory address (or crash on 4MB pages if PSE isn't supported, like on too old CPUs).
Of course requiring that past-4GB address capability breaks compatiblity with older PSE-capable CPUs without the functionality. If the CPU doesn't support it while setting the A32-A35 bits in a large page, it'll start page faulting on the reserved bits instead.

Although PAE is older than PSE-36 as far as I can tell (Pentium Pro and newer). So you'll probably be better off with PAE in that case.