feipoa wrote on 2024-01-23, 08:37:
The unnerving part comes next - I turned the power off, then turned it back on. Measured MCLK and it was still at 48 MHz. Being conservative, I repeated the procedure for MCLK = 51 MHz. Thus, it looks as if the MCLK value get programmed into clock generator and it stays resident. This means that if I wanted to experiment with overclocking MCLK and selected a value which is too fast for the card, the card may no longer be usable. I suppose I could connect the ICD2061A up to an Arduino and figure out the serial programming, but this is hardly worth the effort. Do you know of a simple means to get MCLK programmed back to 50 MHz if MCLK was set too high and will no longer generate a display?
The ICD2061A does not have non-volatile storage. The data sheet lists the power-up frequency selection possiblities, and your card seems to use the setting INIT1=0, INIT0=1, which is supposed to configure the chip to 40MHz MCLK (independent of FSB clock, having 40MHz at both places is just coincidence), and to the standard 25/28MHz video clocks for VGA compatibility. The data sheet explicitly talks about a "power on reset" configuring the chip, so it should revert back to these settings even if you cut the power for just a second. Furthermore, the BIOS unconditionally configures the chip to ~50 MHz during POST. There is no plausible explanation fo the ICD2061A to not revert to 40MHz when you power down the machine, and there is really no plausible explanation for the ICD2061A to not return to 50MHz as soon as the POST of the graphics card is executed. Thus I suspect that your measurements were faulty. Possibly you set the scope to "normal triggering" (instead of the default setting "auto triggering") and lost contact. In that case, the last known good waveform will stay on the screen forever.
Expected behaviour is: As soon as you power-cycle the machine, you will have 40 MHz initialized by the power-on reset circuit of the ICD2061. As soon as the mainboard BIOS hands over to the VGA VIOS, you will get 50MHz, and you only get other frequencies as soon as you run SETMODE MCLK from the DOS prompt. SETMODE CLOCK is close to the most useless feature ever invented, because it just tells you what clock has been last set with this copy of SETMODE.EXE, so the value reported by SETMODE is useless as soon as you push the reset button.
feipoa wrote on 2024-01-23, 08:40:The Cypress datasheet mentions some constraints:
MCLK min: 52 MHz, max: 120 MHz
VCLK min: 65 MHz, max: 165 MHz […]
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The Cypress datasheet mentions some constraints:
MCLK min: 52 MHz, max: 120 MHz
VCLK min: 65 MHz, max: 165 MHz
But we are using MCLK at 50 MHz and... why is VCLK only at 28 MHz? Or is VCLK only of needed from the clock generator if we are using a PLCC-68 RAMDAC?
On the one hand, you misunderstand parts of the data sheet; on the other hand, that box in the Cypress data sheet makes no sense. The IC Designs data sheet mentions different constraint which are at least consistent with the other parts of the data sheet. It generally says f(VCO) should be between 50 and 120 MHz. Let's start with the misunderstanding, though: The data sheet does not specify the minimum frequency of MCLK/VCLK, as you seem to assume. It specifies the frequency of the internal oscillator in the PLL chip (the voltage controlled oscillator), which is used to derive the MCLK/VCLK. The derivation happens by using the "Post-VCO Divisor" (Table 6 in the Cypress data sheet). If you select a Post-VCO divisor of 2, the VCLK range will drop from 50..120MHz to 25..60MHz. As you can select divisors up to 128, you could synthesize frequencies below 500kHz. While Cypress likely bought IC Designs and datasheet revisions correcting minor details might happen, it makes absolutely no sense that the VCO range selection table (Table 7 in the Cypress data sheet) lists a lot of ranges spanning the 50 to 120MHz range (for both the MCLK and VCLK oscillator), and then continues to mention constraints that do not overlap the range selection. I suggest to just ignore the the VCO ranges given in Table 8. I'm not going to argue whether the highest recommendable reference frequency is 25MHz (as the Cypress datasheet claims) or 60MHz (as the IC Designs datasheet claims), because the reference frequency is fixed at 14.318MHz anyway. Furthermore, it is possible that Cypress discovered that the chip has suboptimal performance at reference clocks above 25MHz, so they don't recommend higher frequencies anymore.
You do not need VCLK or MCLK from the clock generator when you use a PLCC-68 RAMDAC: The PLCC-68 RAMDAC integrates its own clock generator. The idea is that you can build cheaper cards (less components) if you use a PLCC-68 RAMDAC instead of having to deal with a PLCC-44 RAMDAC and a dedicated clock chip. So VCLK is only needed if we are not using a PLCC-68 RAMDAC.
feipoa wrote on 2024-01-23, 08:40:Looking at the datasheets and probing some traces on the PCB, I find that differences between the STG1702 (PLCC44) and STG1703 (PLCC68) are that the STG1703 has these extra pins:
(mapping snipped)
To get the PLCC68 STG1703 working, were you suggesting that I isolating STG1703 pins 9 and 61?
Exactly what I expected. The PLCC68 RAMDAC is meant as substitute for both the clock generator and the PLCC44 RAMDAC. I was indeed suggesting to isolate pins 9 and 61. Furthermore, having two chips drive the 14.318MHz crystals may or may not cause issues, depending on how the pins are internally set up in those chips. Isolating pins 6 and 7 as well is a good idea, too. You can't just remove the ICD2061A chip and use the STG1703 clock synthesizer instead, because the BIOS does not support programming clocks in a STG1703 chip, it only supports programming clocks in the ICD2061A chip, and unconditionally assumes the ICD2061A is present.
feipoa wrote on 2024-01-23, 08:40:Is there any tangible benefit to using STG1703 over STG1702? The datasheets indicate that both are 16-bit RAMDACs, yet the datasheet calls the 1703 an upgrade from the 1702. "The 68 PLCC pinout is designed to permit easy upgrade from the STG1700/1702 44 pin PLCC".
I don't expect any benefit. The BIOS won't notice the difference. The BIOS can detect STG DACs. If it detects an STG DAC, it will probe the device ID register, and if it is zero, it treats the DAC at STG1700, and if it is any other value, it treats the DAC as STG1702. As I don't have a comprehensive 1702 data sheet at hand, I can't compare whether the 1703 has better specs, but I can say for sure that the BIOS (as is) will not use any feature of the STG1703 that doesn't work exactly the same way as on the STG1702.
feipoa wrote on 2024-01-23, 08:40:I tried to run my PC Chips M919 with VLB graphics + ISA graphics, but screen stays blank.
That's not surprising: The Video BIOS ROM chip on VLB graphics cards is connected to the ISA bus, and will conflict with the ROM chip on the ISA graphics card. Pulling a ROM chip still isn't likely to work, because usually there is a buffer (digital amplifier) between the BIOS chip and the ISA bus, and even with the BIOS chip removed, the buffer chip will drive something (possibly garbage, possibly all FFh) on the ISA bus.
feipoa wrote on 2024-01-23, 08:40: I then tried to run it with VLB graphics + PCI graphics, but screen stays blank.
This is supposed to "work", but not in the way you want it. A standard 486 BIOS that detects a VGA ROM on the ISA bus (that is a VLB or ISA graphics card) is going to skip initialization of the PCI graphics card (so you will get a blank screen), but the ISA/VLB graphics card is supposed to work. If the PCI graphics card has a "native" operation mode that doesn't interfere with VGA operation, a graphics driver of an operating system might enable that native mode without enabling the compatiblity resources that conflict with the ISA/VLB VGA graphics card, to get both cards running at the same time.
feipoa wrote on 2024-01-23, 08:40:Does anyone know a safe upper-limit for MCLK on an ET4000/w32p?
The ET4000/W32p data sheet I have at hand has the specification of the clock interface in section 4.5. This data sheet uses the name "system clock (SCLK)" instead of "memory clock (MCLK)" to talk about that frequency. The data sheet specification item "F4 (SCLK cycle time)" states: "min. 20ns", so 50MHz is the maximum vendor-permitted MCLK/SCLK, everything above that is overclocking. I don't have any experience about the amount of headroom you have on ET4000/W32p chips, though.
