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Re: UniPCemu cycle accurate 8088 implementation

Posted on 2020-05-24, 22:00

Also, can you explain what happens during the first 2/3 cycles of that OUT instruction? As UniPCemu currently runs it, that weird case without the idle bus cycles will never happen. The first cycle ticks normally. Then, it waits for T1 and on that cycle executes two idle bus states, before starting …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2020-05-24, 19:53

Just have been looking at xtce's code. What's the whole deal with the tFirstIdle and tSecondIdle cycles? Does it have something to do with this current UniPCemu idle bus cycle problem? I don't remember the exact details, but in the process of testing XTCE against XTServer+ISA bus sniffer, I must …

Re: 8088 MPH: We Break All Your Emulators

Posted on 2020-04-05, 10:38

First of all: Happy 5th anniversary to 8088MPH and everyone involved! Thank you! I hadn't realised the anniversary was this weekend. But let's get deeper into the technical details: IIRC the 1024 color mode outputs only the duplicated first scanline of every character row and does that by starting …

Re: Best CGA & Hercules games

Posted on 2020-03-21, 15:55

Technically this game has fantastic effects that I never saw on cga on any other game: https://www.youtube.com/watch?v=SygD93F95js What effects in particular are you thinking of? I didn't notice anything particularly technically interesting about the game, but I'm always on the lookout for new CGA …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2020-03-13, 17:22

What about just splitting the 8088 MPH speed test part into managable chunks for the bus sniffer(of course starting with a jump to get the correct start cache situation)? Like I said, that's the tricky bit. The queue and bus state also need to be in the right state for each instruction. If I can …

Re: 8088 MPH: We Break All Your Emulators

Posted on 2020-03-12, 14:08

Just found out something: CGA applies the memory write waitstates when updating the memory mode(changing mapped memory layout)? So when updating the memory with the new layout(due to changing VGA memory mapping it uses) it sets the waitstate for the current instruction(which it shouldn't)! Not sure …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2020-03-12, 13:55

Do you have some sniffer log of the metric cycle check done at the start of the demo(as well as it's starting address, perhaps the instruction jumping to it for the first time)? Unfortunately that's easier said than done - the ISA bus sniffer only has 2kB of RAM on the ATMega328 microcontroller …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2020-03-12, 12:12

OK. But those 1-cycle startup after the start of IN/OUT, 2-cycle for non-DX IN/OUT BIU idle following that and 1-cycle waitstate on all I/O bus operations is correct? 8088MPH reports 1547 metric cycles now. The PC/XT motherboard imposes a 1-cycle waitstate on all port IO instructions, yes. As for …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2020-03-12, 10:13

I've just been looking at https://github.com/reenigne/reenigne/blob/master/8088/8088.txt again. Pay no attention to that document - it's an older one and the timings there are just from the published ones if I recall correctly. https://github.com/reenigne/reenigne/blob/master/8088/xtce/xtce.h is …

Re: 8088 MPH: We Break All Your Emulators

Posted on 2020-03-09, 09:36

dr.zeissler wrote on 2020-03-09, 07:35: Does this demo work on any other than a cga card? It really needs a genuine IBM CGA card. I think there might be one or two clone CGA cards which have been reported to work as well but it definitely won't work on EGA/VGA/SVGA/later cards.

Re: Raster bar implementation on Amstrad PC1512

Posted on 2020-02-20, 08:08

in Milliways
Yes, I certainly don't expect to get around the memory access wait states. But just to confirm: both types do not halt the CPU. They only tie up the bus, right? If the CPU doesn't need to use the bus, all is ok? They tie up the bus, but when the CPU is doing an IO for the purposes of executing an …

Re: Raster bar implementation on Amstrad PC1512

Posted on 2020-02-19, 14:41

in Milliways
I know what I can do. I can use shl reg, cl instead of nops. Then the CPU won't need to access the bus and I can get variable length instruction timings. Perhaps the CGA wait states are really stopping the CPU from using the bus to prefetch the nops. I should have thought of this earlier. I have …

Re: Raster bar implementation on Amstrad PC1512

Posted on 2020-02-19, 14:35

in Milliways
But that's my point. Where are the CGA wait states? Why can't I run nops during those wait states? Surely wait states only mean the CPU can't access the bus, not that it stops altogether (granted it has to do instruction fetch). I totally get that I can't initiate a stosb and then do a nop while …

Re: Raster bar implementation on Amstrad PC1512

Posted on 2020-02-19, 14:03

in Milliways
That would mean the numbers really don't add up. A raster is 509.6 cpu cycles. If we take 11 cycles for stosw (granted, I used the wrong number here) and just 12 additional cycles for the part of the access not already included in the stosw time, then 7 stosw's and 21 nops should take 161 + 63 = …

Re: Raster bar implementation on Amstrad PC1512

Posted on 2020-02-19, 12:13

in Milliways
I'm totally not convinced the 4 planes take longer. The reason is that in graphics mode 1, the memory for all four planes is written to, but only one of the planes is read. However, reading and writing take the same time. Replacing stosw's with lodsw's makes no difference to timings. But I will …

Re: Raster bar implementation on Amstrad PC1512

Posted on 2020-02-18, 22:21

in Milliways
The RAM is dual ported but that doesn't mean that the two ports are completely independent - the VDU controller still needs to tell the RAM which addresses to send to the raster when. That is easier to do if all the VRAM control logic is derived from the same clock, i.e. the one that comes from the …

Re: Raster bar implementation on Amstrad PC1512

Posted on 2020-02-18, 22:14

in Milliways
The reason why some references say 11 cycles for STOSW and some say 15 is that the former are for 8086 and the latter for 8088 - there is an additional 4-cycle penalty on 8088 due to the narrower bus. STOSW without a REP prefix is documented as being 15 cycles on an 8088, but I measured it as 16 …

Re: Raster bar implementation on Amstrad PC1512

Posted on 2020-02-18, 20:08

in Milliways
Ah, I think I've figured it out. The VRAM in the PC1512 consists of two 41264-15 chips, each 64k x 4 bits. This is dual-port RAM designed for video buffers, with a serial output for the raster as well as random input/output for the CPU. The refresh cycle of the RAM is 4ms (just under 63 scanlines), …

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