Re: HIND Russian Combat Helicopter Simulation error
Posted on 2021-03-05, 19:52
Please share your dosbox.conf.
Re: x86 control transfers and paging faults...
Posted on 2020-12-17, 22:29
That's correct.
Re: x86 control transfers and paging faults...
Posted on 2020-12-07, 17:03
If the access and limit checks pass then registers are committed and the transfer is made. At that point of fetching the new instruction, the page fault is raised.
Re: x86 NULL selector's RPL effect?
Posted on 2020-01-22, 18:19
Loading NULL with any RPL is allowed, since there's nothing to check. ARPL doesn't work on selectors, it's only for registers that you'd move into a selector later. You can load DS with 00. That doesn't introduce any issue because you'll still need to assign a non-zero selector later in order to …
Re: UniPCemu real mode only issues?
Posted on 2019-12-30, 20:26
I'm not sure about the CS limit, but the rest matches my understanding, too. Yes, BIOS interrupts are affected as badly as you expect.
Re: x86 BT* instructions overflow flag?
Posted on 2019-11-18, 16:07
You might get the proper result with RCR/CF=0 but I never tried it. However, they're not the same - RCR with CF=0 introduces a zero-bit where there wasn't one before. If you ROL (not RCL) an 8-bit number by 8 bits, then carry receives a copy of bit 0. If you RCR the same with CF=0, you don't get the …
Re: x86 BT* instructions overflow flag?
Posted on 2019-11-15, 17:10
There are no undefined flags, only undocumented ones. Yes, OF is set up to the Pentium 2 according to some rules. Pentium 2 and later don't touch it. It's set according to the result of ROL of 32 - bit_to_test.
Re: repne/repnz movsw: Invalid instruction prefix mystery
Posted on 2019-08-20, 23:02
I'm not sure if you can actually assemble that code. It's not 'illegal' as such, but it basically doesn't make sense. movs does not modify any flags, so rep is the only sensible instruction to use with it. It depends very much on one thing: if the Z flag was controlled beforehand. cmp dl, 12h repne …
Re: Reason for x86 descriptor type priority over present?
Posted on 2019-08-13, 20:55
I suppose that checking present first might trigger someone to try to bring it into memory before finding that it's not usable anyway.
Re: x86 conforming access rights?
Posted on 2019-04-27, 17:34
It's intended to protect against code returning from low privilege to high privilege, so RPL of 0 and DPL of 3 should fault.
Re: x86 opcodes 0FB7 and 0FBF 16-bit?
Posted on 2019-04-10, 18:56
0FB6 is an 8-bit extension to the operand size. 0FB7 is a 16-bit extension to the operand size. Both can be extended from 16-bit to 32-bit via override (or truncated from 32-bit to 16-bit).
Re: What CPU state is reversed when a fault occurs?
Posted on 2019-03-20, 18:15
How would you determine that? Easy, an interrupt or page fault can cause an exception that allows the flags to be examined. Other relevant registers (esi/edi/ecx) must also be updated on every repeat so the instruction can be resumed properly after an exception. No, that's not every iteration, …
Re: What CPU state is reversed when a fault occurs?
Posted on 2019-03-19, 19:47
EFLAGS Don't think that's right, cmpsb/w and scasb/w with a rep prefix set new flags for every repetition. How would you determine that? It's true for single-step, but otherwise the performance hit to do it on every iteration makes it seem unlikely to me. Certainly on later Pentium CPUs, it's not …
Re: x86 LAHF indeterminated bits?
Posted on 2019-02-27, 19:10
It's the regular bits, just like a PUSHF/POP AX/MOV AH,AL would produce.
Re: Any good MS-DOS 80386/80486 games for testing Virtual memory support?
Posted on 2019-02-13, 20:49
Ultima Underworld, too.
Re: x86 Jcc vs address size?
Posted on 2019-02-13, 20:48
Gosh. Indeed I have it entirely backwards. 0x66 is the override that affects all transfers of control: 9A/E0/E1/E2/E3/E8/E9/EA/EB/7x/0F 8x. There are no exceptions, except that it's 0x66 and not 0x67. That was my mistake. 400000: 66 EB 00 will jump to 0x0003.
Re: x86 Jcc vs address size?
Posted on 2019-02-10, 00:46
So, according to the documentation, operand size (0x66) has effect on the opcodes themselves(e.g. 0F80 being 0x0F80XXXX vs 0x0F80XXXXXXXX), so just changing the immediate operand size. Yes. And with those 0F Jcc (0F80-0F8F) switch between EIP and IP depending on the effective address size( …
Re: x86 Jcc vs address size?
Posted on 2019-02-08, 20:28
Operand size (0x66) will switch between ECX and CX, and 32-bit or 16-bit immediate for 0F Jcc branches). It does nothing for rel8 Jcc. Address size (0x67) will switch between EIP and IP for the destination address if taken, including for rel8 Jcc.
Re: x86 SHLD/SHRD 16-bit count limit?
Posted on 2019-01-22, 19:14
It's likely a typo. The result should indeed be AX=0xFFFFE. i.e. shifting in zeroes.
Re: x86 SHLD/SHRD 16-bit count limit?
Posted on 2019-01-18, 00:55
They're not NOPs. They function as you'd expect, zeroing the register but setting the flags according to the result of the final shift.
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