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Re: Might and Magic Beyond

Posted on 2020-07-16, 02:04

Worked on a lot of gameplay features: houses have proper movies and dialogs now, shops work, guilds (and guild membership) works, opening chests, getting quests, leveling up at trainer and others. Some graphical improvements - working on new look for water: https://i.imgur.com/RtnOyVB.gif Video has …

Might and Magic Beyond

Posted on 2020-07-03, 15:12

Hey folks, I wanted to present a project of mine that occupies my time recently. It is a re-writing from scratch of an engine to play Might and Magic 6, 7 and 8. The engine requires original game data, so you must legally own the game. It is just an executable (plus some data files) that you can …

Re: Dithering emulation?

Posted on 2020-01-29, 15:27

While leileilol is right in that you cannot obtain 100% the same feeling as the HW dithering in old graphics cards, you can get pretty close and maybe do it "better" (quantifying better as in more accurate for the purpose of removing banding) nowadays with shaders (at expense of performance). A …

Re: Preserving segment registers across task switch

Posted on 2020-01-27, 21:41

Thank you superfury. I figured it out (I think). My problem was that when coming out of VM86 via an exception handler, there was no task switch as such (so no previous task link was updated). However that is not needed as after the exception (say general protection fault) the registers all remain …

Re: Preserving segment registers across task switch

Posted on 2020-01-27, 20:15

It seems upon task switch, one of the action the processor takes is this: "Saving the state of the current task. The processor finds the base address of the current TSS cached in the task register. It copies the registers into the current TSS (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, ES, CS, SS, DS, …

Preserving segment registers across task switch

Posted on 2020-01-27, 19:48

So I have 1 TSS set up in my global descriptor table so that when user mode is switching to kernel mode via an INT instruction that TSS is used to set up a) kernel stack (SS0 and ESP0) b) set all segments to the kernel's code and data descriptors. Now on the other side of the INT (once I hit kernel …

Interesting VM86 entering issue

Posted on 2019-11-22, 22:23

So I am trying to write a piece of code that enters VM86. This is done from protected mode with paging enabled. What I do is push the CS, IP and FLAGS (which have VM bit set) and then execute an IRET. I think some emulators(*) (including mine) treat that whole IRET as an atomic unit, but I think …

Re: Protected Mode, IRQs and stack map

Posted on 2019-10-07, 22:55

That's right AFAICT. Except for the ES descriptor typo and ESP+4 should just be ESP, adjusting the others by 4 too. Oh, also the ESP and SS should only be pushed if there's a privilege change. If it's in V86 mode you have to push all the segments and if it's a task gate everything is plopped into …

Protected Mode, IRQs and stack map

Posted on 2019-10-07, 20:40

I am in protected mode, all is set up correctly. IRQ0 (timer) happens. How does the stack look like? I expected it to be like this, but I think that is wrong. Either I am off by 1 or wrong order. [ESP+4] <= EIP of where the CPU was when the IRQ fired [ESP+8] <= CS (descriptor) of where the CPU was …

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