Hi Robin4, today I did some reverse-engineering... For the cache jumpers JP17, JP18 the following configurations work for me (TAG-Chip is always an UMC UM61256FK-15 with 32KByte) : JP17 JP18 1-2 1-2 256kBytes (8x ISSI IS61C256) 1-2 2-3 512kBytes (8x ISSI IS61C512) 2-3 2-3 1MBytes (8x ISSI IS61C1024) …

Hi, I bought the same board on ebay. Thank you very much for the clock speed settings. I spented a lot of time to find this board in the stason database (with the features: 4x ISA, 4xPCI and RTC / Bios between it) but I didn't find anything (also not a similar board). Two hints: - be careful with …