Re: EGA/VGA programming differences and incompatibilities
Posted on 2024-02-23, 02:13
Is Mode F supposed to use the 14Mhz clock?
Re: EGA/VGA programming differences and incompatibilities
Posted on 2024-02-22, 18:43
I implemented pel panning as a fundamental operator of the Attribute Controller. There's nothing to 'latch' per se; when you write a new value to the attribute controller's pel panning register it takes effect immediately. If you maintain a two-character / 16 pixel FIFO, then you can just shift the …
Re: EGA/VGA programming differences and incompatibilities
Posted on 2024-02-22, 18:30
melt (game.exe) in MartyPC: Filename melt_02.gif File size 1.43 MiB Views 829 views File comment MELT effect in MartyPC (click for animated version)
Re: EGA/VGA programming differences and incompatibilities
Posted on 2024-02-21, 14:31
Just have been thinking... UniPCemu latches pixel shift count and byte panning (which are combined) on vertical retrace end (pixel shift count) and vertical retrace start (byte panning). Are those even latched? Or always live? Byte panning btw is counted as pixel shift count addition measured in …
Re: MartyPC
Posted on 2024-02-19, 13:37
Afaik it depends on the pixel mode. During 8 pixel character clocks it MOD 7. So 8-F=0-7. During 9 pixel character clocks 8=0, 0-7=1-8. Above 8 is undocumented. I simply made it 0 there. Perhaps it aliases 1-8 to 9+? You'd need to check real hardware on that. Have you tried FantasyLand in UniPCemu?
Re: MartyPC
Posted on 2024-02-18, 21:36
FantasyLand doesn't seem to use pel panning, which is interesting. It uses the preset row scan register for smooth vertical scrolling, but horizontal scrolling appears character based. Hmm - I'll admit that I was lazy and only looked it up on youtube (https://www.youtube.com/watch?v=czfGt5iNuSQ), …
Re: MartyPC
Posted on 2024-02-18, 19:01
FantasyLand doesn't seem to use pel panning, which is interesting. It uses the preset row scan register for smooth vertical scrolling, but horizontal scrolling appears character based. Just curious, how do you handle the monitor's borders? I get weirdly sized black borders on top,bottom,left,right …
Re: MartyPC
Posted on 2024-02-18, 14:54
FantasyLand doesn't seem to use pel panning, which is interesting. It uses the preset row scan register for smooth vertical scrolling, but horizontal scrolling appears character based.
Re: MartyPC
Posted on 2024-02-18, 12:49
I'm pretty sure FantasyLand does that. It should be a good text mode torture-test in general, although it expects the EGA to be switched to 15.7KHz-only operation (i.e. 200-line text modes). PCjs made a big deal of being able to run it, although it gets the color palette glaringly wrong. :) It runs …
Re: MartyPC
Posted on 2024-02-17, 21:51
EGA support is coming along well. The EGA emulation is character-accurate and the various duties of the various LSI chips are simulated. A similar strategy has been used for EGA as was used for MartyPC's CGA - one of two fixed resolution fields are scanned out (depending on whether the EGA is …
Re: Emulating smooth scrolling in EGA - SOM + Pel panning?
Posted on 2024-02-15, 12:35
keenmaster486 wrote on 2024-02-15, 04:40: I think there's been discussion about this before with reference to clone EGA cards not scrolling Commander Keen correctly. Because they latch the start address at a different time?
Re: Emulating smooth scrolling in EGA - SOM + Pel panning?
Posted on 2024-02-15, 01:11
Well, as soon as I post this, I find this thread: https://www.vogons.org/viewtopic.php?t=57320 Changed from latching the start address at vertical total to latching it at vsync, and now the scrolling is smooth. Imagine that. Would still love to know what the heck the SOM bit is supposed to do, …
Emulating smooth scrolling in EGA - SOM + Pel panning?
Posted on 2024-02-14, 23:36
I'm confused about the SOM field in the End Horizontal Retrace Register. Ferraro has this to say about it: Determines whether an odd or even memory address should be used as the first memory address after a horizontal refresh =0 Start at an even memory address =1 Start at an odd memory address IBM's …
Re: EGA/VGA and mode Fh mono 'colors'?
Posted on 2024-02-11, 20:31
superfury wrote on 2024-02-11, 00:20: GloriousCow wrote on 2024-02-10, 23:44: Can you post your test utility? I can see if it blinks on hardware, if you haven't tested that. https://bitbucket.org/superfury/unipcemu/src/ … niPCemu/pascal/ You'll need UNIPCEMU.PAS and MODE0F.PAS. I was hoping you …
Re: EGA/VGA and mode Fh mono 'colors'?
Posted on 2024-02-10, 23:44
Can you post your test utility? I can see if it blinks on hardware, if you haven't tested that.
Re: EGA/VGA and mode Fh mono 'colors'?
Posted on 2024-02-10, 14:50
It's both inverted and reverted if I'm using the proper terms. On=0, off=1 (=inverted) clock #0=SW#3 and clock #3=SW#0 (=reverted) Otherwise, the IBM documentation on the switches and resulting table entries doesn't match the monochrome modes properly (not selecting 3Bx or aborting in some cases)? …
Re: EGA/VGA and mode Fh mono 'colors'?
Posted on 2024-02-10, 14:21
The EGA BIOS really reads the dipswitches, but practically inverses the bits in the result from the bits in the MISC OUTPUT REGISTER outputs to read it. So clock #0 returns bit #3, clock #1 returns bit #2, clock #2 returns bit #1 and clock #3 returns bit #0 as stored there. So the bits are stored …
Re: The 8088 Prefetch Algorithm
Posted on 2024-02-10, 02:35
What's better than a simple model? An even simpler one! State transitions? Get those out of here! What if absolutely every bus "delay" on the 8088 was simply explained by a 7 cycle bus access time? https://martypc.blogspot.com/2024/02/the-comp … intel-8088.html
Re: 8088 assembly help
Posted on 2024-02-09, 22:20
Even on 8088 its best to use word versus byte if you can, as it saves instruction decode time by just doing half as many (obviously the 8088 can only load/store 8 bits at a time but every saving is worth it). Not to nitpick, but rep movsb is only decoded once (assuming no interrupts occur). The REP …
Re: EGA/VGA and mode Fh mono 'colors'?
Posted on 2024-02-04, 20:14
C0-C3 are of course first masked by Color plane enable before any other processing into an index into the LUT. Right. The color plane enable basically masks the address bits to the attribute palette registers. The documentation mentions it uses C2 and C0 and their combination effects when MONO ( …
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