RayeR wrote on 2024-01-08, 07:39:

Next step further. I managed to disable LPT device block in SuperIO after boot via ISADUMP/ISASET utils ported from Linux to DOS […]
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Next step further.
I managed to disable LPT device block in SuperIO after boot via ISADUMP/ISASET utils ported from Linux to DOS by my friend Ruik
http://rayer.g6.cz/download/download.htm#ISADUMP

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1# konfigurační klíč:
2isaset.exe -f 0x2e 0x87
3isaset.exe -f 0x2e 0x01
4isaset.exe -f 0x2e 0x55
5isaset.exe -f 0x2e 0x55
6# volba logického zařízení č. 3 (LPT)
7isaset.exe 0x2e 0x2f 0x07 0x03
8# vynulování CR 30h
9isaset.exe 0x2e 0x2f 0x30 0x00
10# výpis všech registrů logického zařízení č. 3 pro kontrolu
11isadump.exe -k 0x87,0x01,0x55,0x55 0x2e 0x2f 3

After this HWINFO stopped showing LPT and in IRQ list it shows IRQ 7 as free. The SBPro Test program stills cannot find IRQ but programs using MIDAS library can! So I got sound from Zdoom (no config avail.) and Boost without manual config.

Here I shot one lo-fi quick&dirty video https://www.youtube.com/watch?v=ywgrP-Ki3v4 on a mob.phone, not easy to film one hand and type with other hand, sound is just from overdriven headphones so don't blame quality, it's just for purpose showing the HW setup +init + config sequence...

Congrats on the great success! I would also be very interested in one of these if you are planning to make them available for sale 😎

Oh, I've been fooled... MIDAS actually looks for BLASTER environment variable but as I run my ess.bat under file manager it caused that env. var was not set properly. when I moved setting BLASTER to autoexec.bat (or call ess.bat directly from command shell) then MIDAS properly find the SB resources and use it.

What is success rate of other users? Yesterday I tried to run 12 old demos and only 50% worked with sound. The rest run without sound or stopped due to SB detect error (eveon one demo that I manually setup correct resources) or freezed on start. This is not much positive. So it seems that even after disabling the LPT port some problem still remains. I also got some simple VOCDEMO with src written in Turbopasal that implements some IRQ autodetection routine. It doesn't work too. So I can try debug it to narrow the problem where it freeze...

After playing more with resources I found that IRQ7 for ISA soundcard is some way unreliable even if not shared with anything (I disabled all USB controllers, LAN and LPT and booted from HDD instead of USB flashdisk). It works better with IRQ5 (SBPro test autodetection and some other programs) but I have to disable LPT device after boot by writting to CR30 of SuperIO chip. I cannot disable LPT (set as LPT2 with IRQ5) in setup because otherwise USB controllers will take it (USB 2.0 takes IRQ7 and USB 3.0 takes IRQ5) and there's no other option to keep IRQ5 not used by PCI devices...

This might not be possible, but I found a few chips on modern motherboards that claim eSPI still supports LPC 1.1 via bridge chips such as the ECE1200 or F85227N eSPI to LPC chips.

The ECE1200 eSPI to LPC chip is only like 4 bucks, and could be a pathway to supporting dISApointment with any motherboard with exposed eSPI? I'm imagining an ECE1200 on the dISApointment to connect the motherboard's eSPI instead of LPC/TPM header.

The Asrock B650 LiveMixer motherboard has a special addon card (not released) that takes advantage of eSPI bus to extend the motherboard and uses a NCT6686D chip on the mobo to supply LPC over eSPI. The Asrock X670E Taichi has a similar LPC over eSPI i believe.

I'm interested in getting a 5.25" floppy natively detected on modern consumer motherboards through the Windows 7/10/11 Legacy Drivers. This is pretty much the only way I can imagine it working, and for some reason I still don't think this will work, but am hopeful it will.

dartfrog wrote on 2024-01-26, 07:51:

This might not be possible, but I found a few chips on modern motherboards that claim eSPI still supports LPC 1.1 via bridge chi […]
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This might not be possible, but I found a few chips on modern motherboards that claim eSPI still supports LPC 1.1 via bridge chips such as the ECE1200 or F85227N eSPI to LPC chips.

The ECE1200 eSPI to LPC chip is only like 4 bucks, and could be a pathway to supporting dISApointment with any motherboard with exposed eSPI? I'm imagining an ECE1200 on the dISApointment to connect the motherboard's eSPI instead of LPC/TPM header.

The Asrock B650 LiveMixer motherboard has a special addon card (not released) that takes advantage of eSPI bus to extend the motherboard and uses a NCT6686D chip on the mobo to supply LPC over eSPI. The Asrock X670E Taichi has a similar LPC over eSPI i believe.

I'm interested in getting a 5.25" floppy natively detected on modern consumer motherboards through the Windows 7/10/11 Legacy Drivers. This is pretty much the only way I can imagine it working, and for some reason I still don't think this will work, but am hopeful it will.

eSPI to LPC chips exist, but I don't think there exists one that would somehow emulate LPC DMA.

If the FDC you're going to use can be made work without using the (usually hardwired) DMA2 then you probably still have a chance. I recall seeing someone having asked a similar question here (which I once replied). You may also refer to this.

On the other hand... with older chipsets that still have a complete LPC bus, most complete SuperIO chips do include a FDC and have its LDRQ# wired to the chipset so you could probably try enabling the FDC on the chip and somehow bring the FDC connections out.

I wonder what use case is planned for eSPI to LPC bridges when new MBs are probably using eSPI superIO so nothing else onboard needs LPC. If they just made it for fun for external devices... But still the same problem with missing LDRQ# as on >=1xx chipsets that makes usage limited. No idea how to re-create missing LDRQ# directly from CPU-PCH bus, it wouldn't be easy...

BTW did anyone tried if FDC can work without DMA? I think superIO has some option to enable/disable DMA in FDC block. I don't know how BIOS, DOS, Linux, Windows would handle FDC without DMA. Maybe a custom program could be created to interact with FDC only via IO ports and do e.g. FD from/to images transfer or be loaded as TSR that bypass standard BIOS INT13h routines for FDC...

LSS10999 wrote on 2024-01-26, 14:17:

eSPI to LPC chips exist, but I don't think there exists one that would somehow emulate LPC DMA.

The NCT6796D chip on the Asrock boards I talked about claim it Supports LDRQ#(LPC DMA) and SERIRQ(Serial IRQ) (datasheet link)
The F85226A chip from Fintek also claims it Supports LDRQ#(LPC DMA), SERIRQ(Serial IRQ) (link)
I believe the ECE1200 I mentioned doesn't support LPC DMA, so you're right that not all eSPI to LPC chips are the same. If the LPC DMA is the only foreseeable roadblock and these chips do what they claim, then an ISA slot should work over the eSPI bus through these chips, allowing for full ISA compatibility.

Edit: It seems Intel worked with Microchip to develop the ECE1200 and it does not support eSPI Memory Mastering emulation to Host DRAM, nor the associated LTR command. So LPC DMA isn't supported. That's sad. It seems AMD motherboards are the only potential eSPI candidates from nuvoton's SuperIO line. I know there are other nuvoton chips that support LPC DMA with eSPI, I will compile a list of chips and motherboards that use them, it won't be exhaustive by any means. I suspect there should be other SuperIO chips that have LPC DMA over eSPI, if nuvoton has it. I'll look for other manufacturers too, maybe Intel mobos can be supported if a different SuperIO chip was used, but i doubt it since intel and microchip worked together to make that ece1200 and specifically opted out of LPC DMA. I don't think there is, I think the NCT6796D chip is the only one with a eSPI bus that has support for LPC DMA.

LSS10999 wrote on 2024-01-26, 14:17:

If the FDC you're going to use can be made work without using the (usually hardwired) DMA2 then you probably still have a chance. I recall seeing someone having asked a similar question here (which I once replied). You may also refer to this.

On the other hand... with older chipsets that still have a complete LPC bus, most complete SuperIO chips do include a FDC and have its LDRQ# wired to the chipset so you could probably try enabling the FDC on the chip and somehow bring the FDC connections out.

I'll have to check all that out, thanks. Interesting for sure!

RayeR wrote on 2024-01-26, 16:14:

I wonder what use case is planned for eSPI to LPC bridges when new MBs are probably using eSPI superIO so nothing else onboard needs LPC. If they just made it for fun for external devices... But still the same problem with missing LDRQ# as on >=1xx chipsets that makes usage limited. No idea how to re-create missing LDRQ# directly from CPU-PCH bus, it wouldn't be easy...

Yeah, same here. Fintek claims:

The F85226A is a LPC to ISA Bridge IC for new generation chipset which is no support for ISA bus and slots. However the demand of ISA devices still exists. Therefore LPC to ISA Bridge IC is necessary to be used for new chipset system.

So it seems like legacy hardware use on modern motherboards is the use case? The fact F85226A and NCT6796D claim it supports LPC DMA is honestly wild.

RayeR wrote on 2024-01-26, 16:14:

BTW did anyone tried if FDC can work without DMA? I think superIO has some option to enable/disable DMA in FDC block. I don't know how BIOS, DOS, Linux, Windows would handle FDC without DMA. Maybe a custom program could be created to interact with FDC only via IO ports and do e.g. FD from/to images transfer or be loaded as TSR that bypass standard BIOS INT13h routines for FDC...

Very interesting, definitely going to look up DMA-less FDC, i really had no idea FDC could be without DMA

dartfrog wrote on 2024-01-26, 19:42:

The NCT6796D chip on the Asrock boards I talked about claim it Supports LDRQ#(LPC DMA) and SERIRQ(Serial IRQ) (datasheet link)
The F85226A chip from Fintek also claims it Supports LDRQ#(LPC DMA), SERIRQ(Serial IRQ) (link)
I believe the ECE1200 I mentioned doesn't support LPC DMA, so you're right that not all eSPI to LPC chips are the same. If the LPC DMA is the only foreseeable roadblock and these chips do what they claim, then an ISA slot should work over the eSPI bus through these chips, allowing for full ISA compatibility.

These chips do support LDRQ# on their side (LPC). It's the host (CPU/chipset) that needs to support it somehow.

Modern CPUs/chipsets don't support that anymore. eSPI uses even fewer pins than LPC and by itself no ISA-like DMA, and can be driven with even faster clocks.

I think ECE1200 is the way for eSPI-only hosts to connect to a LPC (mostly SuperIO) device that does not support eSPI, but it does not attempt to emulate LPC features that are now absent. Per ECE1200 datasheet:

5.7.2 PERIPHERAL CHANNEL SUBSET The eSPI Peripheral Channel supports I/O and Memory traffic initiated by the Host System. It doe […]
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5.7.2 PERIPHERAL CHANNEL SUBSET
The eSPI Peripheral Channel supports I/O and Memory traffic initiated by the Host System. It does not support eSPI
Memory Mastering emulation to Host DRAM, nor the associated LTR command.
It therefore does not attempt to re-create legacy LPC DMA or Mastering.

Some chipsets, at least with Intel 100 (Skylake) series, most likely already have an ECE1200 (or similar core) integrated so they can still connect LPC devices just without LDRQ#.

While some new SuperIOs like NCT6796D may support connecting directly to eSPI (so no need for ECE1200 or any integrated bridge) but again, without some kind of external emulation you won't be able to use features in the SuperIO that require ISA DMA (namely FDC or ECP Parallel Port).

dartfrog wrote on 2024-01-26, 19:42:

Very interesting, definitely going to look up DMA-less FDC, i really had no idea FDC could be without DMA

afaik You wont run FDD in modern Windows DMA-less without somehow writing your own driver, and at that point its much easier to just use USB floppy solution from $5 laptop one to Greaseweazle for full support of _all of the formats_.

LSS10999 wrote on 2024-01-27, 01:41:

These chips do support LDRQ# on their side (LPC). It's the host (CPU/chipset) that needs to support it somehow. Modern CPUs/chip […]
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These chips do support LDRQ# on their side (LPC). It's the host (CPU/chipset) that needs to support it somehow.
Modern CPUs/chipsets don't support that anymore. eSPI uses even fewer pins than LPC and by itself no ISA-like DMA, and can be driven with even faster clocks.
Some chipsets, at least with Intel 100 (Skylake) series, most likely already have an ECE1200 (or similar core) integrated so they can still connect LPC devices just without LDRQ#.
While some new SuperIOs like NCT6796D may support connecting directly to eSPI (so no need for ECE1200 or any integrated bridge) but again, without some kind of external emulation you won't be able to use features in the SuperIO that require ISA DMA (namely FDC or ECP Parallel Port).

Yeah, That's why I mentioned those two AMD motherboards from asrock, livemixer and taichi. The cpu Zen (Ryzen) architecture has full LPC support on each die of the multi-die and the block diagram of both motherboards show the SuperIO NCT6686D connected by an LPC bus through a F85227N eSPI to LPC bridge which is directly connected to the cpu socket via eSPI. That's why I figured full ISA compatibility could be achieved because everything in the chain claims to support the full LPC spec.

The thing is though, since the eSPI to LPC bridge chip is communicating with the processor directly via eSPI not LPC. The bridge chip is only talking to the SuperIO NCT6686D via LPC. So I guess my question is, why would the processor itself, need to support LPC? The bridge chip is handling the LPC to eSPI translation and the bridge chip specifically states that's what this chip is for, to enable full LPC spec on cpus that only support eSPI. Maybe I'm missing something obvious?

rasz_pl wrote:

afaik You wont run FDD in modern Windows DMA-less without somehow writing your own driver, and at that point its much easier to just use USB floppy solution from $5 laptop one to Greaseweazle for full support of _all of the formats_.

Yeah I had figured. To be honest it seems an industrial mobo/pc from someone like nixsys is my only real option atm.

~
Also side note, I found this gem from fintek.

Fintek F85526 wrote:

F85526 PCI Express to ISA Bridge IC is necessary to be used for the new chipset system. The issue of the package size is critical for the layout requirement. So the F85526 is the optimal solution for the non-ISA chipset where the package will be the best chosen for economic solution and save the layout size. The two wire signal bus EEPROM interface is provided for the system implementation convenience. Some registers can be pre-programmed via the hardware pin settings to facilitate system initialization. The F85526 absolutely meets PCI Express base spec 1.1 and supports fully ISA interface. Provides multi-ISA compatible slots without buffering and supports ISA parallel IRQ transfer to serial IRQ by IRQ Serialier. It is completely PCIE to ISA bridge specialized chip.

Seems too good to be true, I thought PCIe couldn't be used for an ISA interface?

On block diagram with ECE1200 there's no LDRQ
https://cz.mouser.com/new/microchip/microchip … ece1200-bridge/
and datasheet clearly says:
5.7.2 PERIPHERAL CHANNEL SUBSET
The eSPI Peripheral Channel supports I/O and Memory traffic initiated by the Host System. It does not support eSPI
Memory Mastering emulation to Host DRAM, nor the associated LTR command.
It therefore does not attempt to re-create legacy LPC DMA or Mastering.

I cannot find datasheet for F85227

NCT6686D has LDRQ# on LPC side but it's a qurestion if/what PCH chipset can handle legacy DMA via eSPI.

dartfrog wrote on 2024-01-27, 06:08:

Yeah, That's why I mentioned those two AMD motherboards from asrock, livemixer and taichi. The cpu Zen (Ryzen) architecture has full LPC support on each die of the multi-die and the block diagram of both motherboards show the SuperIO NCT6686D connected by an LPC bus through a F85227N eSPI to LPC bridge which is directly connected to the cpu socket via eSPI. That's why I figured full ISA compatibility could be achieved because everything in the chain claims to support the full LPC spec.

The thing is though, since the eSPI to LPC bridge chip is communicating with the processor directly via eSPI not LPC. The bridge chip is only talking to the SuperIO NCT6686D via LPC. So I guess my question is, why would the processor itself, need to support LPC? The bridge chip is handling the LPC to eSPI translation and the bridge chip specifically states that's what this chip is for, to enable full LPC spec on cpus that only support eSPI. Maybe I'm missing something obvious?

I suppose F85227N is the same as ECE1200, not trying to actively emulate anything. Can't be 100% sure without its datasheet, however.

From what I could find online, LPC is dropped since Raphael (AM5) and Genoa (SP5). They can still be found in AM4/SP4, and in AMD's case, LPC and eSPI are separate.

dartfrog wrote on 2024-01-27, 06:08:

Also side note, I found this gem from fintek.

Fintek F85526 wrote:

F85526 PCI Express to ISA Bridge IC is necessary to be used for the new chipset system. The issue of the package size is critical for the layout requirement. So the F85526 is the optimal solution for the non-ISA chipset where the package will be the best chosen for economic solution and save the layout size. The two wire signal bus EEPROM interface is provided for the system implementation convenience. Some registers can be pre-programmed via the hardware pin settings to facilitate system initialization. The F85526 absolutely meets PCI Express base spec 1.1 and supports fully ISA interface. Provides multi-ISA compatible slots without buffering and supports ISA parallel IRQ transfer to serial IRQ by IRQ Serialier. It is completely PCIE to ISA bridge specialized chip.

Seems too good to be true, I thought PCIe couldn't be used for an ISA interface?

PCIe to ISA was already possible the ITE way using two chips, IT8892E (PCIe-to-PCI) and IT8888 (PCI-to-ISA), which can be found on industrial motherboards with (DMAless) ISA slot.

Just that PC/PCI for DMA was long gone starting with ICH6, and I don't recall any other chipset ever implemented it, so normally no ISA DMA this way.

But this F85526 you mentioned is interesting. Although being on the PCIe bus, it instead relies on LPC to handle DMA!

Fintek F85526 wrote:

PCI Express base spec 1.1 compliant Fully ISA bridge support except bus master (By conditions) IS interface supports 8/16bit I/O […]
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PCI Express base spec 1.1 compliant
Fully ISA bridge support except bus master (By conditions)
IS interface supports 8/16bit I/O R/W, memory R/W and DMA R/W (via LPC interface)
All software transparent
All ISA signals can be isolated
ISA parallel IRQ transfer to serial IRQ by IRQ Serialier
PCIE interrupt supports INTA mode (only for the own device/driver)
Supports multi-slots without buffering
Supports 14MHz output pins
Provide WDT function
Device parameters configurable via EEPROM (ESDA & ESCL interface)
3 sets of address decoder is supported
128pin LQFP package

(Emphasis added)

If this is really true then this chip would be the ultimate answer to the problems with existing ISA bridging methods:
- PCI(e)-ISA is less restrictive when it comes to I/O and IRQ compared to LPC-ISA, but the lack of PC/PCI takes away any possibility to use DMA this way.
- On modern chipsets that still feature a complete LPC bus, LPC DMA is the only way for ISA DMA to work, but accessing the LPC bus can be difficult if the board does not expose it via TPM*.

* Modern TPMs have already transitioned to SPI-based protocols from LPC, so on most chipsets, there's little need to keep LPC anymore now that there are eSPI-compatible SuperIOs.

I wonder if there's any datasheet about this F85526 somewhere...

...and NCT6796D seems to have LPC as a host interface (along eSPI) not for other devices (bridge mode).

...and F85526 spec. explicitly says: ISA interface supports 8/16bit I/O R/W, memory R/W and DMA R/W (via LPC interface)
So it seems it uses PCIe for data but also requires LDRQ# from LPC, so no way... damn't fintek, no datasheet too...

So we are back at the beginning, we need some way to re-create LDRQ some way from CPU interface when not in PCH but it's very fast interface-not easy to do and maybe there sould be collision with existing PCH.

RayeR wrote on 2024-01-27, 06:58:

...and NCT6796D seems to have LPC as a host interface (along eSPI) not for other devices (bridge mode). […]
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...and NCT6796D seems to have LPC as a host interface (along eSPI) not for other devices (bridge mode).

...and F85526 spec. explicitly says: ISA interface supports 8/16bit I/O R/W, memory R/W and DMA R/W (via LPC interface)
So it seems it uses PCIe for data but also requires LDRQ# from LPC, so no way... damn't fintek, no datasheet too...

So we are back at the beginning, we need some way to re-create LDRQ some way from CPU interface when not in PCH but it's very fast interface-not easy to do and maybe there sould be collision with existing PCH.

Yeah, if Fintek could provide some more info about this. But still it's an improvement from LPC-ISA if this is true.

- With this new bridge a hard mod to bring out LDRQ# is all that matters. The rest can be done with a PCIe x1 extension adapter and cable, which can be made in USB 3.0 form (though you cannot connect actual USB 3.0 devices this way). This opens up possibility with AMD 500 series boards on which very few still use LPC-based TPM, while LDRQ0# is still present in AM4 CPUs.
- PCI-ISA is less restrictive about I/O and IRQ and could probably be made work easier than LPC-ISA. While this can be helpful for Intel chipsets that still have LPC bus (up to 9 series), the "firewall" problem with AMD chipsets probably won't make this easier there.

I don't know AMD architecture (and no avail. datasheets for new cpus on theirs site) - does it really route LDRQ directly from the CPU not PCH? So when it cut off on AM5 there's really no way where to get it. Maybe only some emulation in SMM via e.g. NMI or SERR that would be used instead LDRQ...

RayeR wrote on 2024-01-27, 15:00:

I don't know AMD architecture (and no avail. datasheets for new cpus on theirs site) - does it really route LDRQ directly from the CPU not PCH? So when it cut off on AM5 there's really no way where to get it. Maybe only some emulation in SMM via e.g. NMI or SERR that would be used instead LDRQ...

AMD's LPC bridge originally resided in the southbridge (for AM3/AM3+ and before), then in the FCH (for APUs prior to Zen).

Starting with AM4/SP4 the CPU/APU is pretty much a SoC and the FCH became part of the CPU and no longer a separate entity. If you check the AM4/SP4 pin map you'll find LPC related stuffs there.

Hm intel eSPI specification explicitly say this:
LPC Replacement: Supports all the capabilities needed to replace the parallel
LPC interface. However, 8237 DMA and Firmware Hub (FWH) are not
supported over this interface. Even if some kind of bus-mastering is supported but this is a show-stopper 🙁

RayeR wrote on 2024-01-28, 23:43:

Hm intel eSPI specification explicitly say this: LPC Replacement: Supports all the capabilities needed to replace the parallel […]
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Hm intel eSPI specification explicitly say this:
LPC Replacement: Supports all the capabilities needed to replace the parallel
LPC interface. However, 8237 DMA and Firmware Hub (FWH) are not
supported over this interface. Even if some kind of bus-mastering is supported but this is a show-stopper 🙁

I think the 8237 DMA controller indeed no longer exists in modern chipsets anymore. Just checked the 100 series datasheet and found not a single mention of 8237 there.

The datasheet for X99 (which still features LPC) still mentioned the "two cascaded 8237 DMA controllers" as well as LPC DMA.

Of course not a physical 8237 but some emulation logic. And that is missing in eSPI chipsets so it would be only emulated by SW or in SMM. I read Kontron whitepaper mentioned yars ago here about their new AMD system with legacy DMA support and they seemed to really cared about the legacy DMA would work and used some sw hack to achieve this so it gives me that no eSPI chipset would work with any bridge without extra sw emulation support...

I inquiried Fintek for datasheets.
In the a meantime, a question:
Can this adapter be passed to a VM?