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First post, by DosFreak

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https://www.phoronix.com/news/Intel-X86-S-64-bit-Only
https://www.intel.com/content/www/us/en/devel … chitecture.html
https://cdrdv2.intel.com/v1/dl/getContent/776648
https://www.vmware.com/content/dam/digitalmar … tualization.pdf

Supposedly this doesn't affect 32bit software running on a 64bit OS, haven't reviewed it yet.
It'll be interesting to see how this affects virtualization of 16 and 32bit operating systems since IIRC binary translation was removed from virtualbox (6.1.0+) and vmware (14+) (even though the processor still supported it) since they didn't want to support that and only wanted to support VT so with this new standard they would have to emulate these missing functions which is work they have already shown they aren't going to do so expect Virtualbox and Vmware to drop those operating systems when/if this processor is a thing.
QEMU TCG, DOSBox, pcem, bochs will work. Don't know about dosemu.
More work needs to be done for 32bit/64bit (non-UEFI) operating systems pass through (it's ridiculous how piss poor this is), emulation and wrapping of OGL/GDI/ddraw/D3D1-9 to the host on Linux/macOS and Windows that's for damn sure.

2020 – Intel firmware dropped support for running 16-bit/32-bit or non-UEFI operating systems natively.

X86-S ISA External Architectural Specification Document Number 351407-001, Revision 1.0 10 2 Introduction X86-S is a legacy-redu […]
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X86-S ISA
External Architectural Specification
Document Number 351407-001, Revision 1.0 10
2 Introduction
X86-S is a legacy-reduced-OS ISA that removes outdated execution modes and operating system
ISA.
The presence of the X86-S ISA is enumerated by a single, main CPUID feature bit
LEGACY_REDUCED_OS_ISA in a future CPUID field. The bit implies all the ISA removals described
in this document. Some of the additional features, like 64bit SIPI or the 5 Level page table switch,
have separate CPUID feature flags and can be implemented independently of X86-S.
Changes in X86-S ISA consist of:
 restricting the CPU to be always in paged mode
 removing 32-bit ring 0, as well as vm86 mode.
 removing ring 1 and ring 2
 removing 16-bit real and protected modes
 removing 16-bit addressing
 removing fixed MTRRs
 removing user-level I/O and string I/O
 removing CR0 Write-Through mode
 removing legacy FPU control bits in CR0
 removing ring 3 interrupt flag control
 removing obsolete CR access instruction
 rearchitecting INIT/SIPI
 adding a new mechanism to switch between 4- and 5-level page tables
 removing XAPIC and only supporting x2APIC
 removing APIC support for 8529
 removing the disabling of NX or SYSCALL or long mode in the EFER MSR
 removing the #SS and #NP exceptions
 supporting a subset of segmentation architecture, with the following conditions:
o restricted to a subset of IDT event delivery
o base only for FS, GS
o base and limit for GDT, IDT, and TSS
o no limit on data or code fetches in 32-bit mode (similar to 64-bit)
o no AR or unusable selector checking on CS, DS, ES, FS, and GS on data or code
fetches in any mode
o restricted support for far call, far return, far jump, and IRET (like FRED).

A VMM can choose to emulate legacy functionality as required: 1. VMM changes required for mainstream Intel64 guest using legacy […]
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A VMM can choose to emulate legacy functionality as required:
1. VMM changes required for mainstream Intel64 guest using legacy SIPI or non-64-bit boot
a. Emulate 16-bit modes (real mode, virtual 8086 mode)
b. Emulate unpaged modes
c. Emulate legacy INIT/SIPI
2. Optional VMM changes for handling uncommon cases
a. IOPL != 0 (if guest wants ring 3 I/O port access or ring 3 CLI/STI)
i. Catch CLI #GP in CPL3 and emulate
ii. Catch STI #GP in CPL3 and emulate
iii. Catch IN/OUT #GP in CPL3 and emulate
iv. IRET in CPL0 will #GP if attempting to change IOPL, catch and emulate
v. Note that that are un-virtualizable aspects of non-zero IOPL in the next
section.
b. INS/OUTS instructions are removed: Catch #UD and emulate
c. Call gates: VMM needs to catch relevant #GPs and emulate
d. #SS removal: VMM can catch relevant #GPs and report #SS back to guest
e. #NP removal: VMM can catch relevant #GPs and report #NP back to guest
f. CR4.PVI catch and emulate associated #GPs
g. Emulate 16-bit addressing by catching #GPs/#UDs
h. CR4.VME, RFLAGS.VM: Emulate v8086 mode
i. Emulate 32-bit ring 0 and run 32-bit ring 3 with shadow paging in legacy paging
modes
j. Support for unsupported obscure segmentation features like expand down or non
conforming code segments: Can be emulated by catching #GPs
3. Uncommon cases with expensive SW solutions:
a. CPL1/2 requires partial emulation
b. Non-flat CS/DS/ES/SS segments or setting access bits in descriptors in memory
requires full emulation trigged by Descriptor Table Exiting and then setting
GDT/LDT limit to zero (or read/write protect GDT/LDT) to catch segmentation
instructions
c. When EFER.NXE is cleared, a set NX bit in PTE requires shadow paging
d. Segmentation permission checking on load/store/execute: Would require full
emulation
4. Cases that are un-virtualizable
X86-S ISA
External Architectural Specification
Document Number 351407-001, Revision 1.0 28
a. RFLAGS.IOPL != 0: When IOPL is non-zero most cases where behavior would
typically change will instead #GP, which the VMM can catch/emulate (i.e., many
cases are virtualizable). The problematic Intel64 cases are as follows.
i. Ring 0 privileged SW sets IOPL to 3 and changes to ring 3. If ring 3 SW
runs PUSHF or SYSCALL, the value with IOPL=3 should go into the
memory or register destination. When this sequence runs in a VM, the ring
0 instruction that sets IOPL to 3 would cause #GP and trigger a VMExit. If
the VMM resumes the VM with the “wrong” IOPL, i.e., IOPL==0, the ring 3
PUSHF or SYSCALL would expose this incorrect IOPL through memory or
the register. Also, ring3 POPF will not update IF. The preferred scheme is
for VMM to emulate the guest till IOPL is changed back to 0. This case is
not expected on a modern OS.
ii. If the guest attempts to set IOPL to a value greater than zero using a
POPF instruction in ring 0, this will be silently ignored. The IOPL value will
not be updated and the VMM will be unaware that this occurred. Some
subsequent consumers of this value will #GP (e.g., CLI/STI/IN/OUT) but
others will silently continue with different semantics (e.g., IF updating
POPF, memory written by PUSHF, flags stored by SYSCALL, etc.)
b. #UD behavior on SYSCALL/SYSEXIT when EFER.SCE is cleared.

Last edited by DosFreak on 2023-05-20, 13:40. Edited 15 times in total.

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Reply 1 of 30, by Grzyb

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I think I'm experiencing Deja Vu... 80376 ???

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Reply 2 of 30, by Joseph_Joestar

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Itanium's back? 😁

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Reply 3 of 30, by TrashPanda

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Joseph_Joestar wrote on 2023-05-20, 10:20:

Itanium's back? 😁

I hope Intel hasn't decided to move into necromancy, that corpse has been dead and buried for years now.

Funnily enough I do have an Itanium CPU on my display shelf, cant remember how I got it but it sure does look pretty sitting up there with my other tech tinkets.

Reply 5 of 30, by RetroGamer4Ever

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jmarsh wrote on 2023-05-20, 13:24:

This has been coming for a while, the surprising part is that they haven't dropped x87/MMX.

They more or less have dropped x87 and coders/devs are told not to use it for any new applications. MMX is gone entirely from modern hardware, but was folded into AVX, so it can sort of still be used, with code modifications.

Reply 6 of 30, by jmarsh

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RetroGamer4Ever wrote on 2023-05-20, 13:49:

They more or less have dropped x87 and coders/devs are told not to use it for any new applications. MMX is gone entirely from modern hardware, but was folded into AVX, so it can sort of still be used, with code modifications.

It's not gone at all. MMX registers still share the same space as the 80-bit x87 registers and have nothing at all to do with AVX - it is possible to mix AVX and x87/MMX code without any restrictions.

The FPU state is still preserved across threads/tasks in the current windows 11 kernel and this white paper that Intel just released explicitly says the TS bit in CR0 is still usable (for lazy context saving).

Reply 7 of 30, by javispedro1

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VirtualBox actually is trying to bring back binary translation (to run under Apple Silicon). But yes, this is a pretty big deathblow to 16-bit virtualization (and native running...). And likely 32-bit OSes too.

I don't understand why Intel would do this -- the power/performance improvement is likely negligible, albeit there may be some lower testing cost.
However doing this just reminds people that Intel can kill x86 compatibility at any moment, and may make people start thinking about emulation, having software that is less tied to x86, moving to ARM, RISC-V, etc. Just look at the comments of the above articles, which come from people who likely have 0 interest in 16-bit x86, but just see this as the writing on the wall for 32-bit x86.
I see that as much worse for Intel that whatever little they gain by removing any type of "legacy" support.

Reply 8 of 30, by VileR

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Yeah, it's probably not a coincidence that the touted lists of 'benefits' are all benefits for Intel, but make absolutely no difference to the end user. True, a modern 64-bit Intel CPU starts up in real mode. Does that make the slightest bit of practical difference to anyone, besides the fact that it sounds vaguely 'silly' to the average layman?

It'd be nice to know what *actual* improvements people should expect from this (if any), beyond some knee-jerk notion of "removing all this old shit must make it better!". Haven't gone through that entire PDF, but when I hit Ctrl+F and look up 'benefit', 'performance', 'improvement', 'speed', 'fast', nothing turns up.

For instance, I'm aware that one of ARM's major performance edges over x86 is much simpler instruction decoding. But that sort of thing won't be fixed by the proposed update. What will?

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Reply 9 of 30, by LSS10999

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"Using the simplified segmentation model of 64-bit for segmentation support for 32-bit applications, matching what modern operating systems already use."

I wonder if this means under this architecture, 32-bit programs on Windows x64 will be able to access as much memory as 64-bit ones, rather than being capped at ~2GB? If so, it may be helpful in use cases where 32-bit is needed, like having to make use of third-party DLLs that only comes in 32-bit form.

Other than that I don't think there are any apparent benefit. The BIOS in its entirety may need to be rewritten for the new boot sequence that no longer involves any 16/32-bit states, though I'm not sure if this will involve changes to UEFI bootloaders/kernels as well...

But still... looks like VM solutions will have to do more work than before.

Reply 10 of 30, by the3dfxdude

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LSS10999 wrote on 2023-05-21, 14:00:

"Using the simplified segmentation model of 64-bit for segmentation support for 32-bit applications, matching what modern operating systems already use."

I wonder if this means under this architecture, 32-bit programs on Windows x64 will be able to access as much memory as 64-bit ones, rather than being capped at ~2GB? If so, it may be helpful in use cases where 32-bit is needed, like having to make use of third-party DLLs that only comes in 32-bit form.

I don't think that makes sense as if you were to want to access memory using long long pointers, then you'd want to recompile to full 64-bit anyway. There is the ability though, to use 32-bit pointers, and a full mix of 32-bit and 64-bit instructions (again, a recompile, but I guess a partial porting that might be beneficial and easier?):
https://en.wikipedia.org/wiki/X32_ABI

I think if 32-bit protected mode goes away, 32-bit applications could evolve to be more like x32 abi that was proposed. Maybe. I don't know any other reason to keep it.

Reply 12 of 30, by Jo22

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I'm worried about WINE support on Linux.
Linux kernal used to keep 16-Bit/286 Protected Mode support for Windows 3.x applications. Not sure about the recent status, though.

https://news.softpedia.com/news/Linux-Kernel- … ns-447273.shtml

But to be honest, an x86 emulation based on DOSBox would probably do for most casual users.

It's the professionals with real, advanced 16-Bit Windows applications who suffer.
Like AutoSketch 1.x or one of the old 3D modeling programs.

Such programs do still benefit from raw CPU power.
Limiting them to 486 performance levels isn't exactly a nice out sight.

Despite being from the early 90s, they could still work with large data sets and 4k/8k screen resolutions.

But on the other hand, which professional does use Linux? 🙂

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Reply 13 of 30, by LSS10999

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the3dfxdude wrote on 2023-05-21, 14:13:

I don't think that makes sense as if you were to want to access memory using long long pointers, then you'd want to recompile to full 64-bit anyway. There is the ability though, to use 32-bit pointers, and a full mix of 32-bit and 64-bit instructions (again, a recompile, but I guess a partial porting that might be beneficial and easier?):
https://en.wikipedia.org/wiki/X32_ABI

I think if 32-bit protected mode goes away, 32-bit applications could evolve to be more like x32 abi that was proposed. Maybe. I don't know any other reason to keep it.

Back then I had situations requiring some Java code be run with a 32-bit JVM because the project needs to interact with some third-party 32-bit DLLs (which cannot be done with a 64-bit JVM).

As the project may require a lot of RAM I need to specify the amount of memory it's allowed to use via -Xmx parameter. With 64-bit JVM I can specify as much as I deem necessary so long as the system has enough memory, but with 32-bit JVM the maximum I could specify was about 1.2GB and was rather delicate that it would terminate after running for a while and could not be restarted with the same setting anymore. Windows can no longer allocate that much -Xmx to the 32-bit JVM from this point on, even though the system still has an adequate amount of RAM available. Around 1GB was the safe spot for such a use case, though it was barely enough.

So far this is the only case where I ran into the memory limitations for individual 32-bit processes. I haven't tried enabling 4GT yet, though I'm not sure whether 4GT is useful on 64-bit Windows for such scenarios...

Reply 14 of 30, by the3dfxdude

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Jo22 wrote on 2023-05-21, 14:33:

I'm worried about WINE support on Linux.
Linux kernal used to keep 16-Bit/286 Protected Mode support for Windows 3.x applications. Not sure about the recent status, though.

https://news.softpedia.com/news/Linux-Kernel- … ns-447273.shtml

Wine already uses usermode emulation for x86 to run on Apple M1, I believe. So they will probably just do that for all win32 on all platforms. win16 probably will also work the same in Wine, but the future doesn't look that bright for compatibility. There will be alot of work for people like us having new systems fixing stuff all over again. Now I think the intention of the proposal here would still allow something like Wine to run natively, but I am not sure, and I'm not that trusting. Why propose dropping x86 32-bit from being able to boot into, if it really doesn't impact anything at all? I do agree this likely will have a larger impact on a number of applications. Applications likely will break. Maybe they're just getting reading for a completely locked down Windows 12?

Reply 15 of 30, by the3dfxdude

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LSS10999 wrote on 2023-05-21, 14:58:
Back then I had situations requiring some Java code be run with a 32-bit JVM because the project needs to interact with some thi […]
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the3dfxdude wrote on 2023-05-21, 14:13:

I don't think that makes sense as if you were to want to access memory using long long pointers, then you'd want to recompile to full 64-bit anyway. There is the ability though, to use 32-bit pointers, and a full mix of 32-bit and 64-bit instructions (again, a recompile, but I guess a partial porting that might be beneficial and easier?):
https://en.wikipedia.org/wiki/X32_ABI

I think if 32-bit protected mode goes away, 32-bit applications could evolve to be more like x32 abi that was proposed. Maybe. I don't know any other reason to keep it.

Back then I had situations requiring some Java code be run with a 32-bit JVM because the project needs to interact with some third-party 32-bit DLLs (which cannot be done with a 64-bit JVM).

As the project may require a lot of RAM I need to specify the amount of memory it's allowed to use via -Xmx parameter. With 64-bit JVM I can specify as much as I deem necessary so long as the system has enough memory, but with 32-bit JVM the maximum I could specify was about 1.2GB and was rather delicate that it would terminate after running for a while and could not be restarted with the same setting anymore. Windows can no longer allocate that much -Xmx to the 32-bit JVM from this point on, even though the system still has an adequate amount of RAM available. Around 1GB was the safe spot for such a use case, though it was barely enough.

So far this is the only case where I ran into the memory limitations for individual 32-bit processes. I haven't tried enabling 4GT yet, though I'm not sure whether 4GT is useful on 64-bit Windows for such scenarios...

I'm not as familiar with the full capabilities of JVM in 32-bit, but as you said there does seem to be a delicate limit in my experience too. But I don't see this as fixing that problem, and I don't see general applications able to suddenly access more memory. Unless they somehow fix PAE to be as performant up to 64GB as long mode, but if anything, I still think they are likely to break that too, as there isn't much reason to have that around. I would guess that the suggested 32-bit compatibility is for continuing to support things like Wine or Win32 in a 64-bit OS more than actually making anything better, until all that gets forgotten. But I think there will still be a few apps that break if they go forward with whatever is actually removed. The older, the more likely it will, I would guess.

Reply 16 of 30, by Dominus

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the3dfxdude wrote on 2023-05-21, 15:13:
Jo22 wrote on 2023-05-21, 14:33:

I'm worried about WINE support on Linux.
Linux kernal used to keep 16-Bit/286 Protected Mode support for Windows 3.x applications. Not sure about the recent status, though.

https://news.softpedia.com/news/Linux-Kernel- … ns-447273.shtml

Wine already uses usermode emulation for x86 to run on Apple M1, I believe. So they will probably just do that for all win32 on all platforms. win16 probably will also work the same in Wine, but the future doesn't look that bright for compatibility. There will be alot of work for people like us having new systems fixing stuff all over again. Now I think the intention of the proposal here would still allow something like Wine to run natively, but I am not sure, and I'm not that trusting. Why propose dropping x86 32-bit from being able to boot into, if it really doesn't impact anything at all? I do agree this likely will have a larger impact on a number of applications. Applications likely will break. Maybe they're just getting reading for a completely locked down Windows 12?

Not to mention that WINE somehow manages to run 32bit apps on 64bit only macOS machines as well.

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Reply 17 of 30, by DosFreak

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I don't follow macOS much except to boot it in a VM (shock gasp!) to download the macOS equivalent for Steam games so can't provide much detail except for the following.

https://www.codeweavers.com/blog/jwhite/2019/ … of-crossover-19
https://www.codeweavers.com/support/forums/ge … 1836;msg=251836
https://www.codeweavers.com/support/forums/ge … eral/?t=27;msg=

None of this relates to Intel and AMD though since the CPU will still support 32bit code except for where it doesn't as mentioned in the pdf.

I'm suprised they don't lock it behind Intel On-Demand first and see who buys it heh.
https://www.intel.com/content/www/us/en/produ … d/overview.html

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Reply 18 of 30, by LSS10999

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the3dfxdude wrote on 2023-05-21, 15:13:

Maybe they're just getting reading for a completely locked down Windows 12?

Win11 already required TPM2.0, and provided the ability for software to check TPM as well as Secure Boot status (demonstrated by Valorant).

Maybe with Win12 there will be more restrictions and more features for software to check if the system is locked down or not.

Considering they're working on WSA (to run Android stuffs), these features might also be exposed there to provide a SafetyNet-like attestation for apps that want such information.

Per Microsoft's "Windows Hardware Certification Requirements", M$ said this regarding Secure Boot:

"MANDATORY: Enable/Disable Secure Boot. On non-ARM systems, it is required to implement the ability to disable Secure Boot via firmware setup. A physically present user must be allowed to disable Secure Boot via firmware setup without possession of Pkpriv. Programmatic disabling of Secure Boot either during Boot Services or after exiting EFI Boot Services MUST NOT be possible. Disabling Secure MUST NOT be possible on ARM systems."

This was for Windows 8 when it was first introduced, and as of Windows 11 Secure Boot is still not mandatory for non-ARM installation (only TPM2.0, which is not covered here).

So users are not completely locked down and can still choose to disable Secure Boot to install another non-Microsoft OS, even with this new x86S architecture, unless M$ finally decided to amend the certification requirement to remove this mandatory line.

Reply 19 of 30, by the3dfxdude

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Well it's kind of like the ISA slot. They first made it "optional", and things like -5V not needed anymore. One by one the manufacturers decide to pull it out, and change chip sets breaking compatibility (you have no slot, so it doesn't need to work like a full ISA bus). Now about 2020 on, ISA bus signaling is getting removed completely that even integrated legacy stuff is long gone. They deleted that line like about -5V like it never existed in the ATX spec. 16/32-bit is kind of coming to that point, now it will be impossible to support a large portion of the PC's existence. In terms of secure boot being optional, again, that is just a recommendation by Microsoft. All that has to happen is the manufacturers start one by one locking down their products. Even if it is an option, eventually you have no option, and they'll delete that line too, like it never happened. So I probably shouldn't say that Win12 will for sure being the deciding factor, but I'm telling you, many things are starting to line up that the x86 platform is going to soon be radically different. I wonder who will pull the trigger, but it will be very subtle.