feipoa wrote:

Does it run Win98SE and Win2000?

Ive installed win2000 whit the mp6 on the msi board. the 128zx i used for vga did 1920x1080 very crisp, diddent notice any diffrence between later gfx board and the 128xz 😜

Diddent run any tests but when i get the time i will do some everest benchies.

Rise MP6 running at 233 MHz on an i430TX board.

Looking at the benchmarks so far in the 686 test matrix, it's a bit surprising to see the Cyrix FPU as far behind the Pentium as I'd have thought, and not just overall benchmarks, but particularly in the weakest areas for the Cyrix FPU with multiply and divide benchmarks often being better than 1/2 the speed of the Pentium (even though the Cyrix FPU has a 4/6 cycle throughput/latency to the Pentium's 1/3 cycle throughput/latency.
The divide performance wasn't surprising though, being about the same as the pentium of the same clock speed.
Oddly, the 486 (and AMD x5) also kept up much better than they technically should have given the 16 cycle FPU multiply.

Perhaps even stranger, the integer math performance of the Cyrix parts fared slightly worse than the Pentium of the same clock speed in many cases, except for divide oddly enough. OTOH, the I/O performance of the Cyrix chips seem to be where they really shine, except in the case of the Sandra tests where the MII fares no better than the P55C of the same clock speed.
I/O, RAM, and cache performance also seem to be the biggest advantage for the Cyrix 5x86 over the 486.

On a related note, looking at the 486 again here and in the 486 test matrix, it's interesting to note that the 486's floating point multiply is actually faster than the integer multiply (which is also the case for the pentium and appears to be for the Cyrix 5x85 too), but unlike the pentium, the 486 has much faster integer add/subtract than for floating point. In fact, the 486's integer add/subtract performance seems to benchmark relatively close to the 6x86 and Pentium of the same clock speeds, and ahead of the 5x86.

If these integer math benchmark figures accurately translate to real-world application performance, then it would also mean that the 6x86 would have still done relatively poorly in computationally-intensive applications (like 3D games) when compared to a Pentium equivalent to Cyrix PR number since the Pentium's integer math performance would be better too.
However, applications more bottlenecked by RAM or I/O performance would likely favor the Cyrix parts.

That said, those add/subtract/multiply/divide benchmarks are likely a limited sampling of overall performance and are rather vague comparisons. In particular, no distinction of 32 and 16-bit integer operations is made (let alone 8-bit), and likewise for floating point precision. (though I assume single precision 32-bit floating point values were used)

As you have probably just realised, it is very difficult to extract comparative information from the massive test matrix. Things will be much clearer when averaged FPU and ALU bar charts are drawn. I do have a few interesting CPU test results which are not yet on the chart, including a Cyrix MII at 333 MHz. The main take away message for me is that there exists a stable socket 7 Cyrix CPU (MII-333 MHz) which can beat the fastest stable Intel socket 7 CPU (P55C-262 MHz) in Quake 2 scores.

When I get to the super7 set of tests, I'll see how fast I can upclock that MII-400GP. If I were to guess, I would say 350 MHz is the fastest upclock which can complete all the tests, however I do have 4 MII-400GP's to work with, so that should increase the chances of finding the maximum stable upclock.

Now that Jan S. has patched my Biostar 8500TTD socket 7 BIOS for Cyrix 4x support, I was able to take the MII up to 83x4.0, or 333 Mhz. I was also able to run the AMD K6-III+ at 500 MHz without any issues, however I have decided to cap the socket 7 platform at 333 MHz and continue from about 300 Mhz with the Super7 platform. There will be some cross-over, such as the AMD K6III at 83x6.0 (500 MHz) on the socket7 and the MII at 100x2.5 and 95x3 on the Super7.

Due to other meaningful projects I have going at the moment, the timescale for this benchmark comparison may be more in the 2-year ballpark. I hope my equipment will last that long.

feipoa wrote:

As you have probably just realised, it is very difficult to extract comparative information from the massive test matrix. Things will be much clearer when averaged FPU and ALU bar charts are drawn. I do have a few interesting CPU test results which are not yet on the chart, including a Cyrix MII at 333 MHz. The main take away message for me is that there exists a stable socket 7 Cyrix CPU (MII-333 MHz) which can beat the fastest stable Intel socket 7 CPU (P55C-262 MHz) in Quake 2 scores.

Shouldn't the Tillamook be faster still? Or are you including that under SS7?

And on the note of the Tillamook, why limit your testing to the 4x multiplier only, isn't it unlocked for lower multipliers like the P55C? (particularly useful for attempting 100 MHz FSB)

And why not test the P55C at 2.5x 100 MHz?

When I get to the super7 set of tests, I'll see how fast I can upclock that MII-400GP. If I were to guess, I would say 350 MHz is the fastest upclock which can complete all the tests, however I do have 4 MII-400GP's to work with, so that should increase the chances of finding the maximum stable upclock.

If 4x100 doesn't work, but 350 MHz does, you could still try something in-between like 3.5x 112, 95x4, or 4.5x 83. (112 MHz in particular might be interesting with the faster FSB and cache)

Now that Jan S. has patched my Biostar 8500TTD socket 7 BIOS for Cyrix 4x support, I was able to take the MII up to 83x4.0, or 333 Mhz. I was also able to run the AMD K6-III+ at 500 MHz without any issues, however I have decided to cap the socket 7 platform at 333 MHz and continue from about 300 Mhz with the Super7 platform. There will be some cross-over, such as the AMD K6III at 83x6.0 (500 MHz) on the socket7 and the MII at 100x2.5 and 95x3 on the Super7.

Again, referencing Red Hill:
They mention running the K6-III+ 450 routinely at 5x112 MHz with rock-solid stability (on the FIC-503+ -which should be similar for the 503A and PA-2013).

I know ~600 MHz 2+/3+ overclocks aren't uncommon either, but I haven't seen those speeds in the context of routinely applied settings made by dealers.

Similarly, Red Hill mentions commonly setting K6-300s at 3x100 (rather than 4.5x66) with roughly 2 out of 3 chips working perfectly stable at that speed and performing identically to the K6-2/300 for common applications. (non-3DNow!/MMX enhanced stuff)

They generally don't make mention of overclocking lightly either, with few other "routine" cases given. (including Celeron 300A and Intel 486SX-25)
Oddly enough, they don't mention overclocking the K6-2+ at all, even though it fares at least as well than the III+.

I'm not using a Tillamook. Tillamooks have cache issues in socket 7 desktop boards. I'm using a standard Pentium MMX 233. Maybe I'll test it at 2.5x100 for comparison with the MII at 2.5x100. Thanks for that input. If I recall, my Tillamook didn't work properly in my S7 board.

From 285 MHz to 350 MHz is already quite a big overclock for Cyrix CPUs. These tests take a lot of time to complete, so every CPU which gets added ends up sucking ~2 hours, depending on the MHz.

feipoa wrote:

I'm not using a Tillamook. Tillamooks have cache issues in socket 7 desktop boards. I'm using a standard Pentium MMX 233. Maybe I'll test it at 2.5x100 for comparison with the MII at 2.5x100. Thanks for that input. If I recall, my Tillamook didn't work properly in my S7 board.

OK, but you did include the Tillamook in your list to compare on the first page. Or will that be tested in a laptop system?

Do the Embedded Tillamook chips have the same issues as Mobile ones? I've seen stories of people using Pentium Embedded parts in Super 7 systems, with success at 4x100 MHz in some cases. But perhaps that only works for certain boards and/or with a bios flash. (I know the K6-2/III+ parts are like that)

From 285 MHz to 350 MHz is already quite a big overclock for Cyrix CPUs. These tests take a lot of time to complete, so every CPU which gets added ends up sucking ~2 hours, depending on the MHz.

On the more modest end, 3x112 MHz might still be doable, especially if 3.5x100 doesn't pan out.

Also, those PR-400s are all 180 nm parts, right? Were there any 250 nm 400s produced at all?

It's a bit confusing since Cyrix/NS/VIA produced both 250 and 180 nm parts rated for 2.2 V and a rare few at 2.0 or 2.1V (which still may be 250 nm).
This would be important to note since you definitely shouldn't boost the voltage past 2.2 V for 180 nm parts, but overclocking 250 nm parts could merit 2.3~2.5V as used with K6-2s. Though 250 nm Intel overclock guides rarely recommend over 2.3V, albeit those parts are specced for 2.0V in the first place and also used significantly larger dies than the 250nm K6-2 or MII. (not counting the Tillamook, which is smaller than either, though also rated for 1.9/2.0V)

That list was written before I tested out my existing Tillamook. I won't be using a laptop, but if someone else wants to run at Tillamook for all these tests, I'd be happy to add the results.

I doubt any 0.25 micron pieces were ever stamped with PR-400, but I don't know this for certain. The 0.25 micron pieces at 2.2 V were which pieces? The mobile MII's?

feipoa wrote:

That list was written before I tested out my existing Tillamook. I won't be using a laptop, but if someone else wants to run at Tillamook for all these tests, I'd be happy to add the results.

I doubt any 0.25 micron pieces were ever stamped with PR-400, but I don't know this for certain. The 0.25 micron pieces at 2.2 V were which pieces? The mobile MII's?

It seems that the mobile MIIs (both gold and white top) were produced in 250 nm at some point, but 180 nm versions may also exist.

I'd gotten the impression that non-mobile marked 2.2V PR-300, 333, and 366 parts (including the 66x4 333 variant) were produced in 250 nm 2.2V.

It also looks like there was even a 2.2 or 2.0V version of the 66x3 PR-266.

I don't know many details in general about NS/Cyrix switch to 250 nm, but I've seen some articles mentioning that NS was putting heavy priority on getting 180 nm plants online so maybe 250 nm ended up as low priority. That's just a guess though, but it would at least partially explain why Cyrix kept pushing 350 nm parts for so long. (assuming all those 2.9V parts are 350 nm)

But on the note of 250 nm parts reaching 285 MHz (PR-400), it would seem sensible given the fastest 350 nm parts reached 250 and 262.5 MHz at stock rated settings. If they were truly stuck at ~266 MHz, that would imply a much more serious design limitation. As it is, the speeds the MII reached at 2.9V 350 nm tech are rather similar to those achieved by the K6 and Pentium II, albeit those both topped out in 1998 as they were replaced by 250 nm versions.
Plus, the 350 nm K6 also achieved its top speed of 233 MHz at 3.2V, though the smaller die size still kept it below the power consumption of the Pentium II 233 at 2.8V, let alone the 266 or 300.

Oh, I may have confussed 0.25 micron with 0.35 micron and 0.18 micron with 0.25 micron.

I think we'll find this forum a bit slow until Winter comes around again. In Canada, we really treasure our outdoor summer time.

feipoa wrote:

Oh, I may have confussed 0.25 micron with 0.35 micron and 0.18 micron with 0.25 micron.

I think we'll find this forum a bit slow until Winter comes around again. In Canada, we really treasure our outdoor summer time.

Come to Texas, when the asphalt is hot enough to be sticking to the bottom of your boots you will be thinking twice about cold winters.

feipoa wrote:

Oh, I may have confussed 0.25 micron with 0.35 micron and 0.18 micron with 0.25 micron.

OK, I found some more information on Cyrix CPUs here:
http://www.cpushack.com/CyrixID.html

It's a very detailed identification guide that also mentions that all desktop M2 parts were rated for 2.9V except the 180 nm parts. So, apparently all flavors of 350 and 250 nm IBM and NS produced chips are rated at 2.9V (unlike Intel and AMD counterparts with 2.0~2.4V 250 nm parts). There were also the 2.2V 250 nm 6x86 mobile parts.
This would also imply that there were other limiting factors with the M2 that prevented it from scaling better with the transition to 250 nm parts. (which included both 5 and 6 layer processes apparently, and even "6-plus" layers) Except I seem to recall accounts of the 2.2V 250 nm Mobile chips overclocking rather well into the 300+ MHz range (vs the 233-266 MHz rated speeds), so I'm not really sure what to make of this.
Oddly, there's no mention of the .44 and .5 micron 6x86/6x86L parts.

I discovered that my PR366 is actually a 250 nm chip manufactured by NS in the 16th week of 1999. I'm tempted to try it at lower voltages and see what impact there is on stability.

If you can identify any of your chips as 6/6+ layer IBM manufactured chips, it would be interesting to see if those are among the faster clocked (or more overclockable) variants.

And another note on the 6x86/MII in general:
Comments on the Cyrix chips being particularly good at "16-bit" code may really be referring to applications (32-bit instruction heavy or not) on 16-bit OSs (DOS, Win3.x) or 16/32-bit hybrid in win9x. Specifically, there's also the cyrix chips benchmarking well under mid-90s business/office applications, and MS windows itself.

It should be noted that a huge number of such applications were still using Microsoft's outdated compilers optimized for 386/486, and it's quite possible that the 6x86 was better optimized for accelerating old "dirty" (non-pentium-optimized) code, but would potentially fall behind once compilers started catering to newer Intel chips (though there was similarly a lag from P5 to P6 optimized software, and even more dramatic to Netburst later on). The K6 saw this to some extent too, but less extreme.
Since games and some multimedia applications often didn't rely on such outdated compilers and often did some low-level tweaking for further optimization, those types of applications would fare far better on the Pentium. (even more so for FPU-intensive apps)
Also, given Cyrix's smaller marketshare, it would be unlikely for them to get a large portion of optimization specific to their CPUs, so code wouldn't improve proportionally to intel. (some things might get better and others worse depending which areas the 6x86 had in common with Pentium optimization)
That said, most games still catered more to 486 (or 486SX/386 even) up to ~1996. (and 386-specific support is significant to note since the 486 FPU is actually faster at several math operations than the ALU, especially at multiplies . . . at least compared to 32-bit integer multiplication, and 3D games are very multiplier intensive -not sure about 16-bit performance, but that could be a major mitigating factor)

Given the benchmark scores so far, including the break-down of integer math performance, it seems the Cyrix parts don't have a major (or any in some cases) per-clock lead over the Pentium in integer math performance. However, those are also late 90s benchmarks that may be catering more heavily to the pentium and also only seem to show the 32-bit integer math performance, or rather there's no breakdown of 8/16/32-bit integer performance and no accounting for other instructions (various logical and data manipulation/move operations). The cyrix parts certainly seem to have a consistent lead in I/O performance though, comparing chips of similar bus speed.

If we look at these 9 CPUs, could you let me know which fab process you think were employed (.18, .25, .35),

MII-433GP, 2.2V, 100x3 (300 MHz)
MIIv-433GP, 2.2V, 100x3 (300 MHz)
MII-400GP, 2.2V, 95x3 (285 MHz)
MIIv-400GP, 2.2V, 95x3 (285 MHz)
MII-366GP, 2.9V, 100x2.5 (250 MHz)
MIIv-366GP, 2.2V, 100x2.5 (250 MHz)
MII-333GP, 2.9V, 83x3 (250 MHz)
MIIv-333GP, 2.2V, 66x4 (266 MHz, silver-top)
IBM 6x86MX-PR333, 2.9V, 83x3 (250 MHz)

Apparently, those with a "v" after the MII were the mobile editions. I'm not sure what makes them stand out from the non-v desktop variants though. I have all but the top two.

From your monologue, it sounds like that Cyrix 6x86 would have made a decent pre-1996 486-optimised gaming CPU.

feipoa wrote:

If we look at these 9 CPUs, could you let me know which fab process you think were employed (.18, .25, .35), […]
Show full quote

If we look at these 9 CPUs, could you let me know which fab process you think were employed (.18, .25, .35),

MII-433GP, 2.2V, 100x3 (300 MHz)
MIIv-433GP, 2.2V, 100x3 (300 MHz)
MII-400GP, 2.2V, 95x3 (285 MHz)
MIIv-400GP, 2.2V, 95x3 (285 MHz)
MII-366GP, 2.9V, 100x2.5 (250 MHz)
MIIv-366GP, 2.2V, 100x2.5 (250 MHz)
MII-333GP, 2.9V, 83x3 (250 MHz)
MIIv-333GP, 2.2V, 66x4 (266 MHz, silver-top)
IBM 6x86MX-PR333, 2.9V, 83x3 (250 MHz)

Apparently, those with a "v" after the MII were the mobile editions. I'm not sure what makes them stand out from the non-v desktop variants though. I have all but the top two.

From your monologue, it sounds like that Cyrix 6x86 would have made a decent pre-1996 486-optimised gaming CPU.

I'm wondering this also.

But data on this is sketchy. Perhaps the only way to "really" find out is to lift the cpu-caps and have a look at the dies?

feipoa wrote:

If we look at these 9 CPUs, could you let me know which fab process you think were employed (.18, .25, .35), […]
Show full quote

If we look at these 9 CPUs, could you let me know which fab process you think were employed (.18, .25, .35),

MII-433GP, 2.2V, 100x3 (300 MHz)
MIIv-433GP, 2.2V, 100x3 (300 MHz)
MII-400GP, 2.2V, 95x3 (285 MHz)
MIIv-400GP, 2.2V, 95x3 (285 MHz)
MII-366GP, 2.9V, 100x2.5 (250 MHz)
MIIv-366GP, 2.2V, 100x2.5 (250 MHz)
MII-333GP, 2.9V, 83x3 (250 MHz)
MIIv-333GP, 2.2V, 66x4 (266 MHz, silver-top)
IBM 6x86MX-PR333, 2.9V, 83x3 (250 MHz)

Apparently, those with a "v" after the MII were the mobile editions. I'm not sure what makes them stand out from the non-v desktop variants though. I have all but the top two.

Without an actual identification code to look at, I could only guess there.
I can take a crack at some pics of Cyrix chips available online though, like these:
http://www.ukcpu.net/Collection/Processors/Cyrix/MII/MII.asp
and here
http://www.chipdb.org/cat-mii-171.htm

All the 400 and 433 parts (with codes visible) seem to be 180 nm parts from mid/late 1999.
Information on black-top chips is a bit vague, and there's nothing on the white/silver top mobiles in that CPU Shack guide.
There also seems to be less info on the IBM branded parts.

All of the NS produced MIIs seem to be 250 nm, and all from '98 or '99.
Oddly, there's a 3x66 PR266 on the ukcpu page that seems to be an IBM 6 layer 250 nm chip, but has a 9 as the date code, implying 1999, but IBM supposedly wasn't manufacturing MIIs at that point and the guide only goes up to 98 as well. (5=95, 6=96, 7=97, 8=98)

There's a white top PR-300 on chipdb that seems to go by the normal (gold top) NS naming convention and seems to be from 1999, but has an undocumented character (A) for the process. (cpushack lists 1, 2, 7, and B as ?, ?, 250 nm, and 180 nm, but no mention of A at all)

From your monologue, it sounds like that Cyrix 6x86 would have made a decent pre-1996 486-optimised gaming CPU.

Your Doom benchmark figures seem to agree with this too, with the 6x86 PR-200 classic outperforms the P55C-166. Albeit, it also beats the 6x86 @ 150/60 MHz, implying the faster external bus and L2 cache are coming into play.

Depending on the type of game, the advantages would vary, but I'd think the ALU and I/O performance in general would favor the Cyrix parts for 2D drawing tasks at least.

For 3D games using 3D points and polygons (unlike doom) it would be even more interesting to compare for games optimized to work without an FPU (for 386/486SX/DLC/etc) as some 3D engines may rely on 16-bit math for faster vertex calculation. I don't have any raw figures on 16-bit integer math performance on these CPUs, but I'd guess its faster than 32-bit, which is generally rather sluggish . . . and still rather slow even in some much later CPUs (falling behind FPU performance considerably).
Again, I wish that passmark test included breakdowns for 8 and 16-bit integer performance, not just "integer" and "floating point." (which may only address 32-bit integer or may average/weigh mixed scores, not sure)

Pretty much any 3D polygonal games prior to quake would fall into this category of integer-only games. Tie Fighter, Wing Commander 4, and Descent would be among the last of those. Tomb Raider may also do this as it apparently works on FPU-less systems, but I'm not 100% on this and haven't tried it myself.

And on the note of integer based 3D engines, MMX should have accelerated integer (fixed point) based 3D math considerably, and I've seen some references to potential use of it, but little info on actual games/drivers that supported it rather than FP. Fixed point math is a bit more restricting due to the lower precision, but its still quite workable for the most part and MMX should have been considerably faster than FPU even with the fast FPUs on Intel chips. (granted, also quite fast MMX units)

I've sent you CPU scans of my collection. For the 9 CPU's listed, it would be easiest to follow if you could write what fab process you think was employed directly after the CPU listed. If you like, you can refer to the specific CPU scans sent. Check your PM.

All the 400 and 433 parts (with codes visible) seem to be 180 nm parts from mid/late 1999.

Oh, were these not NS-produced parts? Did VIA produce these? This may have been mentioned already and I forgot.

From the information you have provided, here is an initial table. There are still some blanks.

MII-433GP, 2.2V, 100x3 (300 MHz) - 0.18 um
MIIv-433GP, 2.2V, 100x3 (300 MHz) - 0.18 um
MII-400GP, 2.2V, 95x3 (285 MHz) - 0.18 um
MIIv-400GP, 2.2V, 95x3 (285 MHz) - 0.18 um
MII-366GP, 2.9V, 100x2.5 (250 MHz) - 0.25 um
MIIv-366GP, 2.2V, 100x2.5 (250 MHz) - 0.18 um ?
MII-333GP, 2.9V, 83x3 (250 MHz) - 0.25 um
MIIv-333GP, 2.2V, 66x4 (266 MHz, silver-top) - 0.18 um ?
IBM 6x86MX-PR333, 2.9V, 83x3 (250 MHz) - 0.25 um ?

Of your collection, found this with the cpushack guide:

6x86-P90 80 MHz
IBM .65 micron 3-layer, week 3 1996

6x86-P166+ 133 MHz
IBM .65 micron 5-layer, week 13 1996

6x86L PR200+ 150 MHz
IBM .35 micron, week 18 1997

6x86MX PR-233 75x2.5 MHz
IBM .25 micron 6-layer, week 5 1998

MII-333GP 83x3 MHz
NS 1998 week 51

MII-366GP 2.9V
NS process 2 (listed ? in guide), week 9 1999

MII-366GP 2.2V
Hard to make out, but looks like NS 180 nm.

MII-400GP 2.2V
NS 180 nm, week 33 1999

MII-400GP 2.2V
NS 180 nm, week 30 1999

feipoa wrote:

Oh, were these not NS-produced parts? Did VIA produce these? This may have been mentioned already and I forgot.

I seem to remember reading that all the MII parts produced under VIA were actually outsourced to NS. Not sure if this was also the case for any of the Cyrix III/C3s.

In any case, those 400/433 parts match the NS identification code guide on that page.

MII-433GP, 2.2V, 100x3 (300 MHz) - 0.18 um MIIv-433GP, 2.2V, 100x3 (300 MHz) - 0.18 um MII-400GP, 2.2V, 95x3 (285 MHz) - 0.18 um […]
Show full quote

MII-433GP, 2.2V, 100x3 (300 MHz) - 0.18 um
MIIv-433GP, 2.2V, 100x3 (300 MHz) - 0.18 um
MII-400GP, 2.2V, 95x3 (285 MHz) - 0.18 um
MIIv-400GP, 2.2V, 95x3 (285 MHz) - 0.18 um
MII-366GP, 2.9V, 100x2.5 (250 MHz) - 0.25 um
MIIv-366GP, 2.2V, 100x2.5 (250 MHz) - 0.18 um ?
MII-333GP, 2.9V, 83x3 (250 MHz) - 0.25 um
MIIv-333GP, 2.2V, 66x4 (266 MHz, silver-top) - 0.18 um ?
IBM 6x86MX-PR333, 2.9V, 83x3 (250 MHz) - 0.25 um ?

There was a thread on the sysopt forums about overclocking a silver-top Mobile Cyrix 366 where one of the posters mentioned it was a 250 nm part and that the older (2.9V) PR366s were 350 nm, but that seems to conflict with that identification guide.

It's also possible those mobile chips were just special high-grade selections of the 250 nm parts that were otherwise rated for 2.9V.

This also assumes that guide is accurate too, though I'm not sure what sort of non-destructive testing could be used to confirm this. (perhaps attempting to run supposed 250 nm parts at ~2.2V at low clock speeds, since 350 nm parts shouldn't work at all then) You'd probably want an earlier model (definite 350 nm) 6x86MX to compare too with similar voltages. (to make sure it won't run at those settings)

On the destructive end (for someone with access to a collection of dead chips), opening the packages up to compare the die size would be another option. (but, then, you'd also need an accurate guide to die sizes of the various models)

Edit, just saw this on ebay:
http://www.ebay.com/itm/LOT-OF-CYRIX-686-MX-C … =item2a1f7e8573

6x86 PR-200 150 MHz
GEDD7733L
IBM .35 micron 5 layer, week 33 1997

6x86 PR-233 2.5x75
IBM .25 micron 6 layer, rest covered by sticker.

That is certainly possible that the silver-topped mobile Cyrix at 2.2V is really a high end 2.9V version with a lower frequency and your idea to test several 2.9V CPUs at 2.2V and less frequency is a good starting point. A drop of 0.7V quite much though. Unfortunatley, I no longer have capacity to do this as I'm constantly on baby patrol.

So you weren't able to find any info on the last IBM-Cyrix chip?
IBM 6x86MX-PR333, 2.9V, 83x3 (250 MHz) - 0.25 um ?

feipoa wrote:

That is certainly possible that the silver-topped mobile Cyrix at 2.2V is really a high end 2.9V version with a lower frequency and your idea to test several 2.9V CPUs at 2.2V and less frequency is a good starting point. A drop of 0.7V quite much though. Unfortunatley, I no longer have capacity to do this as I'm constantly on baby patrol.

Assuming these really are 250 nm parts, 2.9V would be pretty high in the first place, well beyond the absolute maximum ratings specified by contemporary Intel and AMD parts (K6-2 is at 2.5V iirc).

I'm still a bit dubious as to whether that guide is correct with the 250 nm claims, and that those parts aren't actually 350 nm (or maybe 300 nm). The guide is also missing any mention of .5 or .44 micron process 6x86/6x86L chips, but I've seen numerous mentions of these (including IBM/Cyrix press releases).

I also haven't seen any mention of 300 nm chips or such, just 350, 250, and 180, so it's unlikely that additional in-between processes were used. However, if that guide is partially right on the manufacturing processes, maybe some of those listed as 250 nm 6-layer were actually a 6-layer variant 350 nm process (which would explain the modest speed increases and high voltage).

http://web.archive.org/web/20000831024858/htt … ard/the300s.htm
In their review of the PR300, alternativecpu mentions that the early MIIs were being built on the older 350 nm process (as of early 1998) with plans to transition to 250 nm in May with expected core voltages as low as 1.8V.
http://redhill.net.au/c/c-a.html
Red hill also mentions the PR300 being 250 nm.

X86-guide only lists the PR366 as 250 nm (both a 2.9V example, and a gold-top 2.2V mobile one), but also lists the silver-top 4x66 MHz PR333 mobile as 180 nm. OTOH, that site is also a bit inconsistent with the die-size information on several early 6x86 models and makes no mention of .44 micron early 6x86L parts. The 394 mm2 die listed for .65 nm 6x86s also seems pretty big (bigger than the .8 nm Pentium), but that's not the only source claiming that either.

Red Hill's site

So you weren't able to find any info on the last IBM-Cyrix chip?
IBM 6x86MX-PR333, 2.9V, 83x3 (250 MHz) - 0.25 um ?

That guide provides very little information on deciphering IBM-branded 6x86 chips, unfortunately.

Found an interesting article here:
http://www.maximumpc.com/article/features/old … on_kill_pentium

Especially this page with a variety of benchmarks:
http://www.maximumpc.com/files/u112496/img191_1.jpg

Interestingly, the 166 MHz (PR-200) 6x86MX seems to hold up pretty well to the K6-200 in most of the FPU/gaming applications, and (considering the lower clock speed and weak FPU) not all that far behind the P55C-200 either. (slightly closer than your tests of Quake too, with the 6x86 faring slightly better than the P55C slightly worse)

It's weird that the cyrix chip fares as well as it does and the K6 not so much, since (on paper) the 6x86 FPU should be way behind the K6 (except for a few things, like divide) and the K6 (on paper -and several synthetic benchmarks) should be as fast or slightly faster than the P5 FPU (or P6 FPU, for add/subtract/multiply) with its low latency and high throughput (lower latency than P5 or 6x86, and double the peak throughput of the 6x86).
Maybe there's something else going on, since the more purely FPU-intensive applications (hardware accelerated, not relying on CPU-intensive rendering) puts the K6 in a more favorable light (especially for GL quake and MDK), but the 6x86 is still strangely fast there too. (maybe there's more of a GPU bottleneck?) -Though the 6x86 scored very poorly in the lightwave raytracing test. (while the K6 held up decently against the P55C)

Maybe the divide performance on the K6 FPU is a major liability in some applications. I haven't seen cycle count figures for FDIV execution on the K6, but division wasn't listed among the other (prominently displayed) 2-cycle execution/latency add/sub/mul instructions. (it'll be interesting to see how your K6 benchmarks turn out)
On paper, both the K6 and P5 should outperform the P6 FPU for multiplication, since it's limited to 3/2 cycle latency/throughput vs 3/1 on the P5 and 2/2 on the K6. (ie peak execution would e equal to K6, but latency is higher, while latency is equal to the P5, but throughput is 1/2)

The article also mentions the k6 having better per-clock MMX performance than the P55C (which also the trend in the 133 MHz thread), but the 6x86MX doing very poorly in this area. And even taking the lower clock speed into account, that would still be ~80% the speed of the P55C or K6. That's not all that surprising either though, since the 6x86MX used a relatively basic MMX unit to minimize cost. (not really a bad trade-off considering the relatively limited use of MMX)

This also makes me wonder even more about which might have happened if Cyrix had introduced a socket 5/7 5x86 and/or Media GX derivative (ie socket 7, on-chip peripherals removed, probably bigger cache). Assuming the yields were considerably better than the contemporary 6x86 (which certainly seems to have been the case for the 5x86/6x86 in '95/96), those cut-down Cyrix parts should have scaled up in clock speed much sooner (perhaps keeping up with Intel -which happened with the 5x86 and P5 in '95) though with poorer per-clock performance.
The P-rating of the 5x86 would much better represent FPU performance too (since it would be rated lower than its clock speed)

Some interesting comments from game developers too:
http://www.maximumpc.com/files/u112496/img193_4.jpg

I need to look further into what the latest integer-only 3D games were. I know Wing Commander IV, Descent, and Tie Fighter work on 486SX/386 (without 387), and I think Tomb Raider does too, but I need to confirm that. (if anyone is willing to test this on a 386/486SX system, that would be great) Duke Nukem 3D and various build engine games (along with Doom based games) would fall in a similar category, through they're not using polygonal 3D with projected coordinates.

Those sorts of games would be really interesting to try out on the likes of the K5, K6, or 6x86 against the Pentium.