The chipsets for the two boards look similar.

Well duh, they are identical - 440FX

From what I saw in Everest/AIDA, Intel already set optimal timings.

DRAM Read Burst Timing 2-2-2
DRAM Write Burst Timing 2-2-2
RAS To CAS Delay (tRCD) 1T

The Serpent Rider wrote on 2021-11-01, 19:56:

Well duh, they are identical - 440FX […]
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The chipsets for the two boards look similar.

Well duh, they are identical - 440FX

From what I saw in Everest/AIDA, Intel already set optimal timings.

DRAM Read Burst Timing 2-2-2
DRAM Write Burst Timing 2-2-2
RAS To CAS Delay (tRCD) 1T

Fastest would be RAS To CAS Delay 0. But there is no way to change any of this on the VS440FX unless you manually write to the PCI configuration registers.

I doubt that RAS To CAS delay is available for 50ns on PR440FX or most of 440FX boards.

lol, I said "similar" because I wasn't sure if there was any sub-revision differences.

Yeah, I was thinking to adjust the PCI config registers the same way we did for the NEC Proserva system, but thought I'd ask if anyone had already checked this out. I know the 50 ns jumper setting on the PR440FX offered a pretty decent performance increase. I probably have the results written somewhere.

How much difference would a 0 ws RAS to CAS delay offer?

feipoa wrote on 2021-11-01, 20:36:

🤣, I said "similar" because I wasn't sure if there was any sub-revision differences.

Yeah, I was thinking to adjust the PCI config registers the same way we did for the NEC Proserva system, but thought I'd ask if anyone had already checked this out. I know the 50 ns jumper setting on the PR440FX offered a pretty decent performance increase. I probably have the results written somewhere.

How much difference would a 0 ws RAS to CAS delay offer?

it wasn't huge - something like from 92MB/s to 96MB/s in speedsys IIRC

Did you find that 50 ns was needed to accommodate this change, or was 60 ns suitable in your experience?

I can't answer that exactly. My modules are all rated for 60ns but they test good down to 50ns (or in some cases 45ns) on my Chroma DRAM tester

I can get you an exact figure by twiddling register 58h on my VS440FX tomorrow if you'd like

I'd really appreciate that. Thank you. Are all other registers at their most optimal?

You using a 3202 to test your dram?

I did some testing with NEC Proserva (430HX - P233MMX), which has RAS to CAS set to 3 clocks by default. Fastest is 2 clocks. Using 60 ns EDO.

RAS to CAS = 3 clocks
Speedsys memory = 78.86 mb/s
Quake = 44.1 fps

RAS to CAS = 2 clocks
Speedsys memory = 81.69 mb/s
Quake = 44.5 fps

I then did some testing with VS440FX - PPRO233-512K, which has RAS to CAS set to 1 clock by default. Using 60 ns EDO.

RAS to CAS = 1 clock
Speedsys memory = 91.55 mb/s
Quake = 56.7 fps

RAS to CAS = 0 clock
Speedsys memory = 96.99 mb/s
Quake = 57.1 fps

Next, I did some testing with the PR440FX - PIIOD-333, which has RAS to CAS set to 0 clock by default. Using 50 ns EDO DIMM BUFF. Does this imply that 50 ns is needed for stability w/RAS-to-CAS=0 clocks? What was curious is that RAS precharge is set to 4T by default, whereas I think it was set to 3T on the VS440FX. Why did intel reduce this value?

RAS Precharge = 4T
Speedsys memory = 129.79 mb/s

RAS Precharge = 3T
Speedsys memory = 132.36 mb/s

Questions:
1) Is it safe to adjust the RAS precharge time to 3T on the PR440FX with 50 ns BUFF ECC EDO DIMMs?

2) What response time is necessary for EDO SIMMs to safely use RAS to CAS = 0 clock on the VS440FX?

3) What response time is necessary for EDO SIMMs to safely use RAS to CAS = 2 clocks on a 430HX?

This is from the official 440FX Specification Update from Intel:

2. RAS# to CAS# Delay Should Always Be Set to ‘1’ for Proper Operation The default value of this bit is ‘0’, which allows for th […]
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2. RAS# to CAS# Delay Should Always Be Set to ‘1’ for Proper Operation
The default value of this bit is ‘0’, which allows for the fastest leadoff timing. With this bit set to
‘0’, the current 50 ns and 60 ns DRAMs will have negative timing margins and will result in
problems for sizing and detecting DRAMs. RAS# to CAS# Delay, RCD, should be always set to 1,
which allows for better tRAC and tCSH timing margin.

4. PMC Configuration Register: DRAM Timing Register, Section 3.2.17
The DRAM timing register (address offset 58h), bit 1, should read: RASx# to CASx# Delay
(RCD). 1=Three clocks between the assertion of RASx# and CASx#. 0=Two clocks (default).

So it would appear that RAS to CAS = 2 clocks is actually the fastest setting on all the aforementioned boards. The 1/0 were errata in the original 440FX datasheet.

Further, according to Intel, the value should be set to 3 clocks on both 50ns and 60ns DRAM, although my years of experience seems to refute this assertion.

I'll get you my Chroma model number and verify my speedsys values match yours (I'm 90% sure they do) when I get back to the shop this afternoon.

1) Is it safe to adjust the RAS precharge time to 3T on the PR440FX with 50 ns BUFF ECC EDO DIMMs?

If it works - why not? Although difference is so minuscule, that I personally wouldn't bother.

What response time is necessary for EDO SIMMs to safely use RAS to CAS = 0 clock on the VS440FX?

You need to test particular modules to see what they can tolerate. Some 60ns modules had a lot of overclocking potential and worked fine with 100 Mhz FSB on SuperSocket7 boards. Memory ratings doesn't matter much late into production. For example, we have PC133 SDRAM modules which are capable to work at 200 Mhz CL3 and 166 Mhz at CL2.

maxtherabbit, could you link that errata. I've downloaded 3 pdfs for the 440fx but cannot find what you are looking at.

Based on what you've pasted above, I'm particularly confused at how register 58h, bit1 = 0 = 0ws turns into 2 clocks and how register 58h, bit1 = 1 = 1ws turns into 3 clocks. But sounds like we should leave this on the slowest setting, although with the PR440FX, it defaults to 0 with EDO DIMM BUFF ECC, so I might just leave it. My concern with that MB is the slower precharge time.

I'm not sure how well your numbers will match mine - my CPUs between the two 440FX systems aren't the same. I'll edit the post to reflect which CPUs and speeds I was using.

Here's the DRAM tester:

Here's the VS440FX as configured by the Intel BIOS:

Here's the VS440FX after manually altering register 58h: (All other registers were indeed set optimally by the Intel BIOS)

The errata document is attached to the post. I'm not actually using ECC memory, speedsys is reporting that incorrectly.

Thanks. I was going to ask if you were using the memory in parity, ECC, or neither mode but looks like you've answered that. I suspect ECC mode might be more problematic with RAS to CAS set to "0ws", aka "2 clocks".

The delta is the same between our VS440FX systems.