Here is the result of my measuring of the pins on the bigger ASIC:
B1 = SRAM Bank 1
B2 = SRAM Bank 2
A0 p80-B2, p88-B1
A1 shared p89
A2 shared p90
A3 shared p91
A4 shared p99
A5 shared p100
A6 p76-B2, p81-B1
A7 p75-B2, p82-B1
A8 shared p92
A9 shared p93
A10 shared p94
A11 shared p95
A12 shared p98
A13 p75-B2, p83-B1
A14 p74-B2, p84-B1
A15 p73-B2, p85-B1
A16 p72-B2, p86-B1
output enable (B1&B2): 104
enable B1: 78
enable B2: 80
data: … 54, 55, 56, 57, 58, 59, 62, 63, 64, 65, 66, 67
possibly data: 68, 69
GND: 60, 53, 71, 79, 87, 96
NC: 97, 101
Testpoints on the bottom: 102, 103
I would suspect that the two unconnected lines, that i found earlier were actually data-lines (the patent mentioned 18 data-lines instead of 16). This would explain the blips of I/O that i got on these lines when storing textures into the sram.
Pins 97 may be a address line (i have to check with an oscilloscope) as may be pin 101.
But these pins may be test pins like pins 102 and 103.
One earlier Patent mentioned a 16Mbit 80ns DRAM and the 128K cache.
I would suspect that the earlier version of the card (white magic) did more primitive texturing without filtering and mipmapping.