currently its on auto

that's the reason why - auto configuration uses conservative timings

you now have a single bank configuration with 4*64Kx8 (UM61512)+ 32Kx8 TAG (UM61256)
please try a configuration with all 9 slots 8*32Kx8 (UM61256 / W24257) + 32Kx8 TAG (UM61256) populated (note: jumpers have to be changed to the third line in the manual) - this configuration basically allows tighter timings than the one with 5 slots populated

with 2 bank L2 cache you may try and use 2-1-1-1 read burst at both 33 and 40 MHz and no write waits to L2 cache
and perhaps 0 / 0 waitstates for DRAM

with 1 bank you may need slower timings (2-2-2-2 or 3-1-1-1), at least at 40 MHz

i dont have enough good 32kx8's to do more than 5 slots now. i would have to find some in country. going to drop off now, work time. many thanks

At work now, but with 2-2-2-2 wait 0 i have L1 82.60MB/s L2 46.00MB/s Mem thru 34.35MB/s. i will try 40mhz from the 33 current tomorrow.

Did you try L1 write back & L2 write back?
Try to read and write from and to a floppy disk to verify cache coherency at DMA access.

Got it to run at 40mhz on 2-2-2-2 wait 0. write back L2 is ok, but fails to boot on write back jumper for L1. Bios has it greyed out. The motherboards FDC chip was ripped off so i have to get a i/o card. a lot of the pads and traces are torn out. i have attempted relay the traces and pads but i cannot be 100% i have it correct.

You have PCICLK/3. This setting is for 25 MHz FSB.
Please use PCICLK/4 for 33 MHz and PCICLK/5 (if available) for 40 MHz.

I have no clue about L1 WB setting.

andy120 wrote on 2022-03-26, 06:08:

Got it to run at 40mhz on 2-2-2-2 wait 0. write back L2 is ok, but fails to boot on write back jumper for L1. Bios has it greyed out. The motherboards FDC chip was ripped off so i have to get a i/o card. a lot of the pads and traces are torn out. i have attempted relay the traces and pads but i cannot be 100% i have it correct.

for L2 2-2-2 non-interleaved @40MHz you need data srams with 12ns and tag with 12 ns according to the SIS471 datasheet, so it's good that it is working.
At 33MHz easily 2-1-1 would be possible, but 160MHz with 2-2-2 is for sure faster than 2-1-1 at 133MHz

Yes, L1 WB has to be defined via jumpers.
How did you set the jumpers 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 and 33?

EDIT: typo corrected.

per this except jp21 1-2 (2-3 does not boot) JP15 open, jp16 short, jp17 short (for 40mhz)

have to check 22, 30, 31, 32

andy120 wrote on 2022-03-26, 15:44:

per this except jp21 1-2 (2-3 does not boot) JP15 open, jp16 short, jp17 short (for 40mhz)

have to check 22, 30, 31, 32

🤣 I was looking into this manual:

EDIT: it is similar. Don't know. I was confused about your listing of JP10 and JP11.
So let's assume you have set it correctly.

That was it!!!! 30 ,31 wrong way around!! freeking awesome!
many many thanks!!

Excellent.
On the green line in the first section you can see an L1 cache in WB mode.