wow yeah that is a shit load of logic for a 486 board. Are you sure the ISA bus is working at 8Mhz ? It should be but never know....
Have you followed where each Delay TAP goes ? You could try shorting between a previous TAP and another TAP that leads somehow to an ISA slot.
Shorting the whole thing could make the system very unstable imho. added: each tap drops 10nS from the input clock if I read the datasheet proper.

I've verified the ISA bus is running at 8MHz by sticking a scope on the clock pin in the slot.

I haven't really poked around the delay line chip at all yet, to see which taps are being used or where they go. Decided to make a thread first just in case someone said "no retard that delay line is for XYZ leave it alone"

Its most likely for the ram and screwing with it will not do anything useful
stick the scope on ISA bus while running VIDSPEED.EXE

rasz_pl wrote on 2022-04-03, 10:53:

Its most likely for the ram and screwing with it will not do anything useful
stick the scope on ISA bus while running VIDSPEED.EXE

I've already monitored the ISA clock while flogging the system with various form of video test software. The clock does not modulate

maxtherabbit wrote on 2022-04-02, 19:48:

I've got a pretty neat 486 board here. Built in 1991, it uses a Zymos POACH chipset (designed for 286 systems) grafted to a 486 processor and cache with the help of a bunch of PAL/GALs and discreet logic.

Zymos POACH chipset ? Never heard of it before.
Is that the name for the intel N82230& N82231 combo?
Have you tried using the old AMISETUP program to tweak hidden bios settings/timings ?

Also, a max of 4MB of ram with 16 30p simm slots. That's nice & yucky at the same time 😀

maxtherabbit wrote on 2022-04-03, 12:08:

rasz_pl wrote on 2022-04-03, 10:53:

Its most likely for the ram and screwing with it will not do anything useful
stick the scope on ISA bus while running VIDSPEED.EXE

I've already monitored the ISA clock while flogging the system with various form of video test software. The clock does not modulate

not the clock, check how many cycles read/write strobes last, and how many cycles they repeat. Normal ISA read/write takes 4 cycles with r/w strobe lasting 1 clock cycle.

This would be an impressive early 486 board, if not for the fact its from December 1990 or later (9052 datecode on one of the jellybin chips), >1.5 years after 486 release. This makes it impressively outdated design still being manufactured despite obvious drawbacks and lack of cost optimization 😮.

weedeewee wrote on 2022-04-03, 12:50:

Zymos POACH chipset ? Never heard of it before.
Is that the name for the intel N82230& N82231 combo?

Yes, intel bought the rights from Zymos

weedeewee wrote on 2022-04-03, 12:50:

Have you tried using the old AMISETUP program to tweak hidden bios settings/timings ?

No because I seriously doubt this will bear fruit. This is the 1990 pre-color AMIBIOS, same as you'd see on a 286. The chipset also has no configuration registers at all. There are "additional" BIOS settings to enable/disable the cache and enable/disable ROM shadow, so perhaps there are other configuration bits exposed at an IO port that are implemented in a PAL/GAL though.

weedeewee wrote on 2022-04-03, 12:50:

Also, a max of 4MB of ram with 16 30p simm slots. That's nice & yucky at the same time 😀

I have 16MB in there now (16 1MB sticks)

rasz_pl wrote on 2022-04-03, 13:40:

not the clock, check how many cycles read/write strobes last, and how many cycles they repeat. Normal ISA read/write takes 4 cycles with r/w strobe lasting 1 clock cycle.

For what purpose? I'm willing to examine it if it will help the cause, but since I don't have a real logic probe it will be a pain to set up with just a 4ch scope.

I've attached a dump of the BIOS if anyone is interested to see for themselves

rasz_pl wrote on 2022-04-03, 13:40:

This would be an impressive early 486 board, if not for the fact its from December 1990 or later (9052 datecode on one of the jellybin chips), >1.5 years after 486 release. This makes it impressively outdated design still being manufactured despite obvious drawbacks and lack of cost optimization 😮.

I find its primitive design charming, that's why I'm investing the effort in a build around it

maxtherabbit wrote on 2022-04-03, 18:49:

weedeewee wrote on 2022-04-03, 12:50:

Zymos POACH chipset ? Never heard of it before.
Is that the name for the intel N82230& N82231 combo?

Yes, intel bought the rights from Zymos

Interesting, never knew that.

maxtherabbit wrote on 2022-04-03, 18:49:

weedeewee wrote on 2022-04-03, 12:50:

Have you tried using the old AMISETUP program to tweak hidden bios settings/timings ?

No because I seriously doubt this will bear fruit. This is the 1990 pre-color AMIBIOS, same as you'd see on a 286. The chipset also has no configuration registers at all. There are "additional" BIOS settings to enable/disable the cache and enable/disable ROM shadow, so perhaps there are other configuration bits exposed at an IO port that are implemented in a PAL/GAL though.

whatever goes for a datasheet, only 37 pages, does mention that IO and RAM waitstates can be altered, though no mention of how exactly to change them. default 1 for ram, 4 for IO.

edit: maybe the info can be found in the "Intel 286EX Application Note", though good luck finding that 😒

maxtherabbit wrote on 2022-04-03, 18:49:

weedeewee wrote on 2022-04-03, 12:50:

Also, a max of 4MB of ram with 16 30p simm slots. That's nice & yucky at the same time 😀

I have 16MB in there now (16 1MB sticks)

and again I let myself get tricked by the datasheet mentioning 4Mb Ram refresh and thinking it applies to 4MB, urgh
oh well. thanks for the correction!

maxtherabbit wrote on 2022-04-03, 18:51:

rasz_pl wrote on 2022-04-03, 13:40:

not the clock, check how many cycles read/write strobes last, and how many cycles they repeat. Normal ISA read/write takes 4 cycles with r/w strobe lasting 1 clock cycle.

For what purpose? I'm willing to examine it if it will help the cause, but since I don't have a real logic probe it will be a pain to set up with just a 4ch scope.

as long as its a storage scope even 2 channels are fine. Grab Clock and one of the R/W strobes, count cycles during long read/write, this will let you see where the slowness comes from (rarer transactions or artificial waitstates) http://www.ee.nmt.edu/~rison/ee352_fall09/PC104timing.pdf

weedeewee wrote on 2022-04-03, 19:25:

whatever goes for a datasheet, only 37 pages, does mention that IO and RAM waitstates can be altered, though no mention of how exactly to change them. default 1 for ram, 4 for IO.

4 waitstates would make every transfer take 8 cycles = half the throughput like you are seeing.

You said your et4000 got 4mb/sec on your 286. What speed are the isa slots running at in that setup?

Anonymous Coward wrote on 2022-04-04, 02:59:

You said your et4000 got 4mb/sec on your 286. What speed are the isa slots running at in that setup?

10MHz

Yes it's faster, no that doesn't explain the situation. All ISA cards I've tried vastly underpeform on this board. Doom scores are way below par for a 486-33 despite good memory and cache numbers in speedsys

rasz_pl wrote on 2022-04-04, 02:28:

maxtherabbit wrote on 2022-04-03, 18:51:

rasz_pl wrote on 2022-04-03, 13:40:

not the clock, check how many cycles read/write strobes last, and how many cycles they repeat. Normal ISA read/write takes 4 cycles with r/w strobe lasting 1 clock cycle.

For what purpose? I'm willing to examine it if it will help the cause, but since I don't have a real logic probe it will be a pain to set up with just a 4ch scope.

as long as its a storage scope even 2 channels are fine. Grab Clock and one of the R/W strobes, count cycles during long read/write, this will let you see where the slowness comes from (rarer transactions or artificial waitstates) http://www.ee.nmt.edu/~rison/ee352_fall09/PC104timing.pdf

I see what you're after. Based on the observed behavior, I'm almost certain the answer is "rarer transactions" but I will verify to be sure. My gut is telling me the glue logic is forcing 3 cycles of the 33MHz processor clock in I/O recovery time.

rasz_pl wrote on 2022-04-03, 13:40:

weedeewee wrote on 2022-04-03, 19:25:

whatever goes for a datasheet, only 37 pages, does mention that IO and RAM waitstates can be altered, though no mention of how exactly to change them. default 1 for ram, 4 for IO.

4 waitstates would make every transfer take 8 cycles = half the throughput like you are seeing.

The way I read that part of the datasheet is with the understanding that all AT-bus derivative systems can "alter" the number of inserted waitstates in the same fashion - through assertions of 0WS# and IOCHRDY

I found the board on Ultimate Retro
https://www.ultimateretro.net/en/motherboards/6702

Unfortunately the listing doesn't offer any documentation. The DIP switch for the memory size does seem to conform to this similar listing, with the exception of the absence of the SW1/5 switch and the associated memory configurations involving 4MB SIMMs.
https://www.ultimateretro.net/en/motherboards/3382

I'm really starting to get curious about the unpopulated DIP-16 footprint below the memory size switch bank. Perhaps this was intended for another DIP switch bank controlling additional configuration options in hardware?

maxtherabbit wrote on 2022-04-03, 18:49:

weedeewee wrote on 2022-04-03, 12:50:

Zymos POACH chipset ? Never heard of it before.
Is that the name for the intel N82230& N82231 combo?

Yes, intel bought the rights from Zymos

You absolutely sure of that?

I only know Zymos as a bottom-feeding chipset relabeler; just lke PC Chips later would, they just slapped their name on other peoples' silicon. I have (or had, not 100% sure if it's still here) an ISA VGA card with "Zymos Poach 51 AA" chipset, which in fact is a Trident TVGA8800CS. If they slap the exact same name on an otherwise Intel chipset, I'd be sceptical of them being the original designers...

maxtherabbit wrote on 2022-04-04, 03:19:

rasz_pl wrote on 2022-04-04, 02:28:

as long as its a storage scope even 2 channels are fine. Grab Clock and one of the R/W strobes, count cycles during long read/write, this will let you see where the slowness comes from (rarer transactions or artificial waitstates) http://www.ee.nmt.edu/~rison/ee352_fall09/PC104timing.pdf

I see what you're after. Based on the observed behavior, I'm almost certain the answer is "rarer transactions" but I will verify to be sure. My gut is telling me the glue logic is forcing 3 cycles of the 33MHz processor clock in I/O recovery time.

By that do you mean that there is a period of dead time in between the (otherwise normal length) ISA bus cycles?

dionb wrote on 2022-04-04, 06:04:

maxtherabbit wrote on 2022-04-03, 18:49:

weedeewee wrote on 2022-04-03, 12:50:

Zymos POACH chipset ? Never heard of it before.
Is that the name for the intel N82230& N82231 combo?

Yes, intel bought the rights from Zymos

You absolutely sure of that?

I only know Zymos as a bottom-feeding chipset relabeler; just lke PC Chips later would, they just slapped their name on other peoples' silicon. I have (or had, not 100% sure if it's still here) an ISA VGA card with "Zymos Poach 51 AA" chipset, which in fact is a Trident TVGA8800CS. If they slap the exact same name on an otherwise Intel chipset, I'd be sceptical of them being the original designers...

I guess I can't say I am "absolutely" sure, but the intel branded POACH chips say copyright zymos on them, you can see for yourself in the picture in the OP

bakemono wrote on 2022-04-04, 09:52:

maxtherabbit wrote on 2022-04-04, 03:19:

rasz_pl wrote on 2022-04-04, 02:28:

as long as its a storage scope even 2 channels are fine. Grab Clock and one of the R/W strobes, count cycles during long read/write, this will let you see where the slowness comes from (rarer transactions or artificial waitstates) http://www.ee.nmt.edu/~rison/ee352_fall09/PC104timing.pdf

I see what you're after. Based on the observed behavior, I'm almost certain the answer is "rarer transactions" but I will verify to be sure. My gut is telling me the glue logic is forcing 3 cycles of the 33MHz processor clock in I/O recovery time.

By that do you mean that there is a period of dead time in between the (otherwise normal length) ISA bus cycles?

Yes. At least that is my operating assumption, I need to verify with the scope.