feipoa wrote on 2022-09-14, 20:48:

What we definitely want to get rid of is JP1. VCC5 should always be 5 V, regardless of the version of SXL CPU used. I can see people confusing JP1 for bypassing the VRM, which it does not do.

I agree the naming is confusing and we need to solve that. But the voltage on pin J1 of the processor is something we have to be clear on. There is a difference between SXL versions here. According to the manual; for all SXL processors (including the one you intend to use) pin J1 needs to be VCC3 - NOT VCC5! ....BUT, for the 'G' variants of the processor pin J1 needs to be VCC5. Now these seem to be rare (never seen a picture), so you could argue not to bother with them, and the associated jumper.

feipoa wrote on 2022-09-15, 07:23:

Looking really slick. yes, I was planning on finding a way to get a more precise measurement either this evening or the next.

EDIT: How much of an overlap does it say there is?

Not much, about the width of a processor pin.

It is entirely possible that the courtyard is wrong. Just get me your measurements and we will use them, but make every effort to get down to the thousand of a inch if you can.

Btw, can you give measurements in thousands of inch, switching back and forth between metric and imperial causes small errors. So I have been converting your measurements on google. 😀

Blavius wrote on 2022-09-15, 07:26:

feipoa wrote on 2022-09-14, 20:48:

What we definitely want to get rid of is JP1. VCC5 should always be 5 V, regardless of the version of SXL CPU used. I can see people confusing JP1 for bypassing the VRM, which it does not do.

I agree the naming is confusing and we need to solve that. But the voltage on pin J1 of the processor is something we have to be clear on. There is a difference between SXL versions here. According to the manual; for all SXL processors (including the one you intend to use) pin J1 needs to be VCC3 - NOT VCC5! ....BUT, for the 'G' variants of the processor pin J1 needs to be VCC5. Now these seem to be rare (never seen a picture), so you could argue not to bother with them, and the associated jumper.

I’m not in front of it anymore.

Do you see an error on the pin designations/trace routing?

I haven’t ran any traces on the overhang so not there yet, but if there are errors in the socket routing let me know as those should be going to the right places already. I just have to tidy up the paths they are taking a little 🤣.

You guys may wanna take a close look at the screenshots and verify every trace is going to the right counterpart. I am going off the nets from the other pcb project. Kicad says it is right but if there was an error in the footprint it won’t know the difference.

Do you see an error on the pin designations/trace routing?

On your last version I see JP1 is gone. Just wondering what you connected pin J1 to instead (VCC3 or VCC5)

Btw, feiopa. If you wanna open up my latest screenshot in paint and draw the traces on that overhang it would save me time when I get a chance to mess with it again. (Save me from having to study the datasheets to see what goes where on that fet 🤣) Don’t draw any traces for vcc5, vcc3 or gnd. Just point them out with arrow. Those are already on planes.

Where is the memw# pin? I don’t see it on the net list.

Blavius wrote on 2022-09-15, 07:38:

Do you see an error on the pin designations/trace routing?

On your last version I see JP1 is gone. Just wondering what you connected pin J1 to instead (VCC3 or VCC5)

Nothing yet. Waiting on the layout to be decided.

Please clarify which j1

J1 of socket? J1 of fet?

Please clarify which j1

J1 of socket? J1 of fet?

J1 of the socket.

Blavius wrote on 2022-09-15, 07:46:

Please clarify which j1

J1 of socket? J1 of fet?

J1 of the socket.

No connection routed yet. Where do you want it to go? Vcc3?

There are a number of other pins not going anywhere

J1
F1
A5
A3
A10
A17
B17
B15
D17
D16
C11
C14
C12
H15
L15
G15
Q17
R16
N3
H3

At quick glance.

Anything you want me to do with these?

Blavius wrote on 2022-09-15, 07:26:

feipoa wrote on 2022-09-14, 20:48:

What we definitely want to get rid of is JP1. VCC5 should always be 5 V, regardless of the version of SXL CPU used. I can see people confusing JP1 for bypassing the VRM, which it does not do.

I agree the naming is confusing and we need to solve that. But the voltage on pin J1 of the processor is something we have to be clear on. There is a difference between SXL versions here. According to the manual; for all SXL processors (including the one you intend to use) pin J1 needs to be VCC3 - NOT VCC5! ....BUT, for the 'G' variants of the processor pin J1 needs to be VCC5. Now these seem to be rare (never seen a picture), so you could argue not to bother with them, and the associated jumper.

Blavius, I'm not sure what these non-G variant 3.x volt SXL2 chips are. You may have a typo in your above statement. You've said that the processor I intend to use requires J1 set to VCC3. However, we are using the G variant in this upgrade, as shown in previous posts.

I have a QFP144 SXL2-66 3.6V with part number TI486SXL2-G66-HBN on a commercial adapter. VCC5 (J1) is set to 5 V on this unit (measured with DMM). The 3.6V chip intended for the adapter at hand now has part number TI486SXL2-G66-GA. Both these are G variants.

QFP144 photo: download/file.php?id=43455&mode=view
PGA168 photo (to be used in this adapter): download/file.php?id=43454&mode=view

Manual states, "This pin is VCC5 for the T1486SXL-G40 and TI486SXL2-G50. It is VCC for all other devices." Thus we should eliminate JP1.

Sphere: I will need to do some desolder to get a better measurement, but will get it done.

Sphere478 wrote on 2022-09-15, 07:30:

Btw, can you give measurements in thousands of inch, switching back and forth between metric and imperial causes small errors. So I have been converting your measurements on google. :-)

Lol! I was wondering how on earth you are using inches for these measurements - it seems so unnatural to me.

Regarding the VCC5 pin, which is location J1 on the PGA-168 grid, this pin should go permanently to 5 V, not VCC3. See discussion above.

Regarding traces for VRM, trimmer, etc, it should be the same as what's on Blavius' layout, with his R1 resistor going to pins 1 & 2 of the trim pot.

J1 is VCC5. It is the only pin on the PGA-168 that should be 5 V (not 3 volts).

Listed in the manual are the no-connect pins (nc). Their grid locations (terminal numbers) are:

A3
A5
A14
A17
B14
B15
B17
C10
C12
C14
D16
D17
F1
G15
H3
H15
J17
L15
N3
Q15
Q16
Q17
R16

In addition, there are two other pins which should not be connected. They are:
A10 - manual states this is reserved
C11 - this is the FLT#. It has an internal pull-up.

You have most of these in the list you provided, but surprisingly, missing from your list were:
A14
A17
B14
C10
J17
Q15
Q16
Where are these guys headed?

feipoa wrote on 2022-09-15, 08:07:

Blavius, I'm not sure what these non-G variant 3.x volt SXL2 chips are. You may have a typo in your above statement. You've sai […]
Show full quote

Blavius, I'm not sure what these non-G variant 3.x volt SXL2 chips are. You may have a typo in your above statement. You've said that the processor I intend to use requires J1 set to VCC3. However, we are using the G variant in this upgrade, as shown in previous posts.

I have a QFP144 SXL2-66 3.6V with part number TI486SXL2-G66-HBN on a commercial adapter. VCC5 (J1) is set to 5 V on this unit (measured with DMM). The 3.6V chip intended for the adapter at hand now has part number TI486SXL2-G66-GA. Both these are G variants.

QFP144 photo: download/file.php?id=43455&mode=view
PGA168 photo (to be used in this adapter): download/file.php?id=43454&mode=view

Manual states, "This pin is VCC5 for the T1486SXL-G40 and TI486SXL2-G50. It is VCC for all other devices." Thus we should eliminate JP1.

Ah! I missed your processor is also a 'G'. In that case I completely agree with your take. Sphere, please forget what I said and go with Feipoa regarding J1 😀

Here is the GIMP'd markup of your layout that you requested.

I'm not sure whether it matters or not, but I measured the factory heatsink, which is 1.75 inches by 1.75 inches.

EDIT: The ceramic of the CPU also measures 1.75"x1.75". So we'd want the backside of the VRM to line up with the edge of the CPU/Heatsink. The manual for the VRM states that the distance from the VRM's pin to the flat side of the VRM is 0.1", or 2.54 mm. You can use this measurement to line up the VRM's holes. Perhaps we'd want to space it out an additional 0.5 - 0.75 mm (.02" - .03") to allow for heatsink placement tolerances?

EDIT2: And looking at the physical dimensions of a PGA-168 CPU, the distance from the CPU's outer pin to the edge of the ceramic is nominally 0.07".

EDIT3: So taking these dimensions to determine the centre-pin (PGA168) to centre-pin (VRM), we get 0.1"+0.07", plus say 0.03" (allows for tolerance), we arrive at 0.20", or 5.08 mm. I think this is a good distance. Does the layout complain about overlap still? If so, I wonder what the PGA-168 dimensions are being used?

What is the resistance value of r2 and the current the trace between trim pot, fet, and r2 will experience? basically no current I assume?

It would be very little. I can check spec sheet notes, but cannot do that until much later when kids asleep.

R2 is 121 ohms
Trim pot is 23o ohms for the desired 3.6 v output.

okay even direct short to 5v it is 4 percent of a watt on r2 🤣. so nothing. The trace there can be whatever we want width wise.

I've spent the last 30 min having my time wasted by jlcpcb after they told me to set up the design constraints wrong.

Figured it out though and confirmed minimum clearances/settings. the clearances are so tight on this board that I wanted to confirm I had the minimum possible clearances at my disposal when routing. Now I can continue attacking the hundreds of DRCs on this spaghetti bowl of a board 🤣. I can't impress how cramped this board is, but it is still looking like I'll be able to get everything routed. there is still hours of work left to do on the signal traces.

Good news though is the overhang is mostly setup.

because of the use of power planes the only trace that I really needed to run is the one we talked about. all the others are already there or a via away. 😀

It seems that r2 and trim r1, all they do is provide a reference voltage to the regulator. So I don’t think the regulator pulls any power from these at all, just senses it. You could in theory even use higher values intel did something similar to this for bf0/bf1

Intel speced as high as 500 ohm/2100ohm

the resistors themselves basically are in series and short between VCCx and vss(gnd) and the middle is a tunable voltage reference.

So speaking of this, are you sure that the trim pot isn’t supposed to be hooked to voltage source vcc5? Because tuning a reference from the voltage you are trying to make seems weird..?

Just to give you an idea of how much work there is left to do, I have to make all those arrows go away still. FML. Lol most are easy to solve though. Move a trace here, move a via there, re route this here, re route that there. And after all that, hope that that didn’t screw up the ground planes too bad.

I’m pretty confident at this point that any hope of equal trace length is out the window. There just isn’t the room for it.

Solved the DRCs in this corner to show you it’s possible. Still have to come back to it though and optimize the flood plane and make the angles and lengths tidy and consistent. I also gotta do some pondering about via size, minimum is 0.2mm hole 0.45mm diameter 0.13 annular (I converted the board to mm btw)

These are small enough to work, but a larger via may give better current. But how big can I go and make it all work? Do I make some small and some big depending on clearance? Or keep all one size.

The via setup used on the previous board violated JLCPCB DRCs so I can’t use them.

Minimum size:

Standard kicad via:

Via used on previous board:

I have a correction from earlier btw, I mistook the markings on the top socket as belonging to the lower socket in the interior, in fact the two sockets are not clocked the same direction. One is 90* off from the other. I added pin one markers to prevent further mistake.

Here is a close up of the overhang.

Verify that the holes are labeled for correct voltage and that the single lonely trace 🤣 goes where you want.

To clarify the thru holes labeled to a specific voltage are connecting to the layer of that voltage. (So no trace needed) smd pads get vias to connect.

I just added j1 hardwire to vcc5 (5v) (doesn't need a switch?)

there is no connection on
a10
C11
As you said.

The rest of your list looks accurate.

Confirmed discrepancies aren’t going anywhere. My list was just a quick glance, not a full accounting. But looking closer, Everything appears as you describe it. So I think we are okay on unused pins.

Can you confirm that all signals seem to be going to the correct pins on respective sockets. They are, as far as the nets are concerned, just wanna make sure the nets are accurate.

Fet spacing is 5.5 currently.

just Moved fet to 5.08mm spacing center to center

In terms of the current between VRM's Vout and GND thru R1/R2, expect around 10 mA. With Vout = 3.6 volts, and Iadj negligible, then V=RI ==> I = V/R = 3.6/(R1+R2) = 3.6/(121+230) =~ 10 mA. There are caveats with going too low with these, as well as too high. Min load currents being one. I cannot remember them all, but from what I recall, it is best to use values in the approx. range of what is in the datasheet. Each manufacturer is slightly different here.

It has been many years since I built my prototype and I had tested several linear and switching regulators and landed on this MIC29302WT. I did some load tests with what might be a typical current to the CPU, and at 730 mA, VRM does not get hot, just a little warm. At 360 mA, was at about room temperature. I think that was after 10 minutes.

The trim pot should not be connected to Vcc5. The Input of the VRM should be connected to VCC5.

Dang, there's a lot of arrows. Isn't there an auto route feature?

Sphere I have no doubt you will be able to route this board - but how will you assemble it? Two overlapping through hole sockets seem impossible to hand solder...