There is a more than 10-fold increase in cost when going from 6-layer to 8-layer? The values you quoted, $7 is 6-layer at 5 units, or $1.4/PCB and 8-layer is $86 for 8-layer at 5 units = $17.2/PCB. Is that right?

I'm stating to wonder if using two PCB approach may help the situation if a 6-layer board cannot be realised. Does cramping all these traces so close together create too much cross-talk for the unit to work well? A realistic goal for CLK2 would be 90 MHz.

I've been playing around with my stacked unit on an MS-3131 motherboard shown here:

Best I can get it to run at is 75.0 MHz. I tried 3 different CPUs. I'm guessing the stacking and trace lengths is limiting MHz. I need to run it on more motherboards to be sure though. I know the Evergreen SXL2-66 I tested could do 80 Mhz easy. I think I also ran it at 87.5 MHz without issue.

I tested Blavius' board, but system would not turn on, even at 16 MHz. I need to test more motherboards. Not sure why it worked on his system.

I just posted a 6 layer design. 😀

I reverted back to 6 layer.

Stay tuned for next version. Beta soon.

On the other design. Try adding wires to jump gaps on the power planes. There seems to be errors on power plane propagation.

Sphere478 wrote on 2022-09-30, 09:25:

I just posted a 6 layer design. :-) […]
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I just posted a 6 layer design. :-)

I reverted back to 6 layer.

Stay tuned for next version. Beta soon.

On the other design. Try adding wires to jump gaps on the power planes. There seems to be errors on power plane propagation.

Looks like you posted that while I was already writing my reply, so I missed it.

Okay, pick this apart, point out any errors you see, and tell me if you want any changes.

continued

feipoa wrote on 2022-09-30, 08:50:

I tested Blavius' board, but system would not turn on, even at 16 MHz. I need to test more motherboards. Not sure why it worked on his system.

Sorry to hear that man. What processor are you using? For me it works with the SXL-40 at 20MHz base clock. Your soldering looks fine. Do you get a reasonable voltage out of the regulator? Only thing I can come up with is you could try changing JP1 to VCC instead of 5V, just to see what that does - in my case its on VCC.

It seems like it should be on vcc5. what does datasheet say?

in the meanwhile I have been further tweaking the routing. Mainly the orange layer. nothing of real significance though.

The next beta might be prototype worthy. I'd like to get everyone's scrutiny on beta 3.14. check it for errors, see if you have any suggestions. There are a few more tweaks left to do but nothing significant that I see.

Sphere478 wrote on 2022-09-30, 20:33:

It seems like it should be on vcc5. what does datasheet say?

The data sheet says for pin J1:
VCC5: TI486SXL-G40 and TI486SXL-G50
VCC3: everything else

As you can see the manual does not specify anything for the TI486SXL-G66. Might not have been out at the time. The assumption so far has been it would follow the same trend and need VCC5 on pin J1, but it doesn't hurt to try it at VCC3, to see if it makes it work. Its also relevant for the design you're making.

Should we bring back the solder jumper?

Looks nice. Hope it works. Are you expecting me to go one-by-one on each trace again? That was rather painful on the eyes the last time I did this.

I can try J1 on Vcc3, but I think the chance that this is the problem is slim. I'm also not able to get my original prototype working on the same motherboard I showed in earlier posts that it worked. Re: Custom interposer module for TI486SXL2-66 PGA168 to PGA132 - HELP! I will probably need to check each pin one by one. My prototype had J1 on 5V for the SXL2-G66 CPU. I will also need to hunt down the same ISA cards shown in that photo. Maybe even the same memory sticks.

I also tried running the adapter with a 5V SXL2-50 rather than the G66 chip, but issue was the same. I upped the voltage to 4.8 V using the trimmer when using the 5V SXL2 chip. I will need to spend more time with this. It will probably take a week or two.

I tested the G66 CPUs in my other adapter so I know the CPUs are functional. Also, J1 is set to 5 V on this adapter, while Vcc at 3.6 V.

EDIT: Yes, I checked the voltage to the CPU. I attached leads to the Vcc and Vss pins on the PGA168 CPU that were furthest from the VRM and I measured 3.60 V. I also measured 5.02 V to the VRM's input.

EDIT2: Thinking back 5 years, I do recall this board being finicky with SXL chips, like the ISA cards would only work in particular slots on the ISA bus.

feipoa wrote on 2022-10-01, 11:30:

Looks nice. Hope it works. Are you expecting me to go one-by-one on each trace again? That was rather painful on the eyes the la […]
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Looks nice. Hope it works. Are you expecting me to go one-by-one on each trace again? That was rather painful on the eyes the last time I did this.

I can try J1 on Vcc3, but I think the chance that this is the problem is slim. I'm also not able to get my original prototype working on the same motherboard I showed in earlier posts that it worked. Re: Custom interposer module for TI486SXL2-66 PGA168 to PGA132 - HELP! I will probably need to check each pin one by one. My prototype had J1 on 5V for the SXL2-G66 CPU. I will also need to hunt down the same ISA cards shown in that photo. Maybe even the same memory sticks.

I also tried running the adapter with a 5V SXL2-50 rather than the G66 chip, but issue was the same. I upped the voltage to 4.8 V using the trimmer when using the 5V SXL2 chip. I will need to spend more time with this. It will probably take a week or two.

I tested the G66 CPUs in my other adapter, so I know they work.

EDIT: Yes, I checked the voltage to the CPU. I attached leads to the Vcc and Vss pins on the PGA168 CPU that were furthest from the VRM and I measured 3.60 V. I also measured 5.02 V to the VRM's input.

EDIT2: Thinking back 5 years, I do recall this board being finicky with SXL chips, like the ISA cards would only work in particular slots on the ISA bus.

The nets haven’t changed. So they should all be going to the same places. One would imagine re checking wouldn’t be needed. As the program gives me a line for each net. It is probably sufficient that you checked those on the previous version.

I’m bummed that I wasn’t able to get more isolation on the trace runs or equal length. But this is just what we are gonna have to do as the other ideas didn’t work out. If I do equal length we will loose all sorts of ground plane conductivity. And route traces by all sorts of interfering signals. Worse so than it already is.

I was at least able to minimize vias on this version and make traces larger.

The power planes look really good also.

So maybe one more beta and prototype it.

I’m hoping others can take a look and make suggestions for the next beta though, pool our brainpower, try out inprovments/ideas.

I think we have something pretty close to the best possible thru hole design here.

A smd version may be able to do better.

Soon it will be on you to solder this thing. 😀 hope you are successful. Doesn’t look fun.

What is the closest trace-to-trace distance a) on the same layer, b) between layers? I was wondering to what extent this would need to be optimised, given the difficulty with the earlier prototypes?

Length wise There are a few that jump one pin over. And many that go across the socket diagonally.

We start making traces longer and we are going to loose ground plane integrity and just pick up more interference.

Making a very small number of the shortest traces a tiny bit longer without too much chaos may be possible, but I say we prototype as is before sacrificing more ground plane integrity. You may be able to hit the clocks you want as is.

As far as how close they get to other things they are about 0.25mm from any object on a given plane. Stack distance will vary by pcb thickness. So thicker may be better. But difference may not be noticable.

I may be mistaken, but it looks like your reply is about trace lengths. I was wondering what is the shortest gap is between traces, that is, how wide is the dialectric spacing between the edge of trace A to that of trace B.

See edit^ 😀

Btw,

I added back the option for 5v and 3v reference for the pot. On the underside.

Any other features we want?

Little more tinkering and checking and I’ll drop beta 3.141.

We can decide if we should prototype at that point.

All the DRCs are solved except for a glitch with overlap on socket courtyards. But we can ignore that. There isn’t an actual problem there.

I'm not sure what you mean by "reference for the pot". If you are referring to Blavius' solder bridge jumper, calling it "pot reference" is confusing. That SMD jumper only set the voltage for one single pin on PGA168, pin location J1; nothing else. It is not for bypassing the VRM, it doesn't set the CPU's running voltage, or anything like that. If this is indeed what you are referring to, it would be better to call it J1 voltage with the options being 5 V and VRM., or even 5V and 3.6V, but as 3.6V is variable, the former is probably preferred. If you want to include it, might be better to have it as a through-hole jumper/header, but probably isn't enough space, so solder pad it is.

Sorry, I’m talking about where the regulator references its voltage from. It seems odd to reference from the very voltage it is making.

If there is any use for changing the j1 voltage let me know, Many processors maintain a vcc5 pin when they went to 3.3v even socket 5/7 had this. So it makes sense that there would be a vcc5 pin on the socket. Socket 3 also had one. Why it would need to be 3.3v is odd. But let me know.

It wouldn’t take much of anything to add a solder switch on the back for j1 also.

Edit:
I see in the datasheet that you uploaded earlier in the thread that it shows in the example circuit that the pull up resistor is attached to vcc3.

I suppose if the datasheet likes it, then it should be fine. So I’ll remove the addition.

Want me to add back j1? Be easy to put it on the back, won’t take any space really.

You are referring to the 1.25 V reference voltage that is generated between Vout and ADJ on the pins of the MIC29302WT? Yes the VRM generates its own reference from the 5V input voltage, but this is fairly common. I'm not sure what you are proposing to do differently.

feipoa wrote on 2022-10-02, 05:46:

You are referring to the 1.25 V reference voltage that is generated between Vout and ADJ on the pins of the MIC29302WT? Yes the VRM generates its own reference from the 5V input voltage, but this is fairly common. I'm not sure what you are proposing to do differently.

It’s all good, I’m gonna take it back off after looking at the datasheet you uploaded earlier.

I can add a similar switch for j1 pretty easy on the back of the adapter. Won’t take up any space of consiquence.

The Microchip datasheet doesn't talk a whole lot about the reference voltage. Usually stuff from Texas Instruments provide a lot more details. More on it in this TI LM1085 datasheet, but not exactly a lesson book. Although, TI does provide some great free learning tools and pdfs, e.g. their short course on PLLs, filter design, caps for regs, etc.