Check if you have working reset on power-good signal from PSU. And/or use a reset button connected to the mobo header - you should have RESET LED on your POST card, that should change state shortly after power-on and when the button is pressed. Note that it's not the same signal but ISA reset follows mobo reset.

With a scope you can check for activity on the BIOS ROM chip, at least one of the /CE and /OE lines should be toggling (the other is most likely wired to GND permanently). Check for presence of clock signal on CPU and again note that ISA has it's own clock but both should be present. LED on POST card is only lit on low state of the ISA clock line IIRC, doesn't really mean it's toggling (or the correct frequency).

I attached a couple photos I made illustrating my understanding about tracing signal activity using an o'scope on processor CLK. Do you place a probe on the solder joint for the pin for CLK? Pin RESET is also shown.

Similarly the EPROM picture shows E not and G not/VPP. These are Chip Enable and Output Enable/Voltage Supply. You mentioned looking for a signal on CE? Could the OE signal be the opposite of connected to ground, since it is ties to Voltage Supply (VPP) instead?

Why does it seem like the "Test Access Port" is not available on motherboards for average consumers? The Intel 486 had diagnostic functions located in package/microprocessor housing. Motherboards had a TAP or Test Access Port. I bet these were only on engineering reference motherboards.

Yes, you can probe at the CPU pins, just be careful not to short anything with the probe tip. If you need to look at several signal, or want a more permanent setup, just solder a short wire from the socket pin and clip the probe to that. Pick a nearby GND for reference, you can also solder a wire. Running the GND for the probe from far away will inject tons of noise into measurement (usually it's noise below switching points of digital logic but it can be confusing, so best to avoid it).

BTW TAP is only for the pin state scan, I'm not sure if it can be even used with the CPU working at full speed. I've seen some 286 and 386 mobos with (usually not populated) headers or unmasked pads for tesing some important CPU signals, but not on 486 and never anything JTAG/TAP. You could try soldering wires to CPU socket for that too but IIRC not all 486 CPUs had this implemented.

As for the EPROM, the /E is indeed chip enable/select signal, and /G is output enable. It doubles as Vpp for programming but different EPROM parts require different driving. In some cases, when Vpp is a separate pin, it needs to be tied to Vcc for correct operation (though on some chips it doesn't matter), here it need to be pulled low for output so obviously it can be at Vcc level then. So it only needs logic H to disable output but not power on that pin. During programming you send pulses at Vpp (12V or higher, depends on the chip) to store data into the array but the mobo will never do that.
It might be that /E or /G is permanently tied to GND and only the other one is connected, that is how many mobos do it, so don't be surprised. This can be easily tested with ohm meter without power applied.

I am waiting on a low insertion force PGA socket to arrive by mail. I believe the LIF will make probing tiny ZIF socket holes easier. When it does I plan to resume testing. But for now the ZIF socket has a burn mark at hole for CLK. I was using staples and a set of helping hands I got off Amaz*n . Clamping to a staple with my probe, I got CLK and VSS mixed up. I also found out that I will have to ensure that I know how to use my scope to get a square wave. I have considered using a wave form generator to see if I can pick up a 33 MHz square wave. I tried reversing my scope leads so the probe was on CLK. I had a cycle but it was distorted, I don't think shorting your 5V CLK to ground causes CLK to be distorted. Rather no cycle would be shown on oscilloscope. However clearly I need experience adjusting my scope for reading CLK.

I wanted to mention that your replies helped me gather understanding at a time when I had never done the things I thought about. I also learned to probe areas of the motherboard I had not before. For example, before you told me to check output enable and chip enable, I was considering a mixed signal probe and the data out pins. I was going to use DSO storage, look back, and decode the bits to see if the words matched what showed in the first lines in programmer software window. I was well aware how time consuming this would be. But how do you find clues from the BIOS chip? That was when I saw your message and realized I could use OE and CE instead. I could now get evidence that the CPU was accessing the EPROM.

I will be back when I have finished where I left off, which was the staple going white hot. I have a LIF on the way. No more staples. Just my probes in a 268 pin PGA LIF socket and my Amaz*n helping hands. This should make testing easier as contacts on LIF are a larger target.