http://web.archive.org/web/20050214165907/htt … snet.co.za/k7m/

here is a download location for the last release.
http://dlsvr01.asus.com/pub/ASUS/beta/mb/bios/km132.zip

Possible source for the AMI 8.27.13 flash utility
http://zakrzewski.tk/bios.html

Here are a few, but I think that for anything earlier than 1006, you'll need a dump off of a chip.

Thank you! I'll try all of those! 😀

mockingbird wrote:

Here are a few, but I think that for anything earlier than 1006, you'll need a dump off of a chip. […]
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Here are a few, but I think that for anything earlier than 1006, you'll need a dump off of a chip.

km1006.zip

km1209.zip

km1008.zip

1008 version was probably the one I had before, I'm back with my old benchmark scores and stability, thank you again 😀

What problems did you have with the other versions you've run? Do you know which chipset revision you have?

swaaye wrote:

What problems did you have with the other versions you've run? Do you know which chipset revision you have?

I have board rev 1.04. I've yet to lift the HS on the NB, so I don't know exactly what chipset revision it is, but it's a newer one since it has super bypass.

The problem I had was that one version, 1007, gave me one less MHz in FSB overclock (from 107 down to 106). The other two, 132 beta (latest) and 1009 gave me less 3DMark99 score, down från ~8100 to ~7700. Don't ask me why, have not seen such difference in any board ever just from changing bios version. 1008 is clearly the winner with stability at 107 MHz and higher score in 3DMark.

Are you aware of the Irongates "Super Bypass" mode for memory access? (chipset revision C5 or newer)
Most BIOSes activate it when TRCD <3 and TRC <8.
Safe Default timings are: TCL 3, TRP 3, TRCD 3, TRC 8, TRAS 7, PH 32, IC 8 cycles.

Also: http://www.heise.de/ct/hotline/Speicher-Timin … rds-307644.html (may req. translate)

elianda wrote:

Are you aware of the Irongates "Super Bypass" mode for memory access? (chipset revision C5 or newer) Most BIOSes activate it whe […]
Show full quote

Are you aware of the Irongates "Super Bypass" mode for memory access? (chipset revision C5 or newer)
Most BIOSes activate it when TRCD <3 and TRC <8.
Safe Default timings are: TCL 3, TRP 3, TRCD 3, TRC 8, TRAS 7, PH 32, IC 8 cycles.

Also: http://www.heise.de/ct/hotline/Speicher-Timin … rds-307644.html (may req. translate)

I'm not sure what you want to say? You mean that the instability could be caused by super bypass? I have RAMs capable of 170+ MHz in CL2 installed now. I could also enable and disable super bypass, so it's not something I cannot control. What I've read, you should have super bypass enabled for the extra performance.

I wanted to say that for super bypass to work you need to set memory timing values within certain limits.
I also wanted to quote that the irongate could have stability problems with RAMs.

I didn't know about the timing restrictions with Super Bypass. That could explain some stability problems I've seen.

It is possible RAM timings can decrease board stability, I guess it depends on the PCB layout. Luckily my MS-6195 can run CL2-2-2-2 (with Super Bypass enabled) just fine.... well, or at least it is stable enough for 2 hour long SuperPI run. 😀

http://hwbot.org/submission/3088193_havli_sup … 3min_2sec_338ms