First post, by jbenam
Hi everyone,
I've got a GMB-486SG which is very dear to me - and I've put an Am5x86 X5 P75 on it. I've got the last revision of the board (v2.2, according to the sticker onboard) and the latest available BIOS around, which it seems is 01/10/95.
I'm not sure what is going wrong, but I have been able to get the L1 Cache Write Back mode only a few times. Everything works wonderfully with L1 WT.
I am looking at the latest manual available: http://minuszerodegrees.net/manuals/Gemlight/ … tion%206.03.pdf
I have spent the good part of today in trying to document the "CPU" jumpers. The manual just gives you a bunch of stuff without explaining what it does - something that I hate, since I can't tweak anything nor try to pinpoint the issue with the WB cache mode.
Here are my current findings:
JP21
Hardware trap, according to the SiS471 schematics. Not sure what this is about.
JP24
5-6 = 4x Multiplier
Open = 3x Multiplier
JP30
1-2 = L1 Write Back
2-3 = L1 Write Through
Open = L1 Write Through
JP35
Closed = 5v
Open = 3.3v
JP36
In 3.3 Mode:
1-2 = 3.3V
2-3 = 3.5
Open = 4V
Random stuff I've found out with a multimeter:
JP25
Pin 1 - JP31 Pin 3, JP13, Pin3
Pin 2 - W/R* Chipset
JP31
Pin 1 - JP10 Pin 1
Pin 2 - CACHE# CPU
Pin 3 - JP25 Pin 1
JP12
Pin 1 - HITM Chipset
Pin 2 - HITM CPU
JP13
Pin 2 - INV CPU
Pin 4 - INV CPU
JP15
Pin 3 - WB/WT# CPU
Funny thing is, I can pretty much leave out every jumper from the "left" CPU block and the system still boots and performs as if following the AMD X5 config in the manual. What is the purpose of these jumpers then? Maybe they just have "sane" defaults when Open?
Anyway, I know that the "right" block (JP34, JP6, JP10, JP11) has at least something to do with L2, since removing everything disables L2 completely.
Anyone else with any experience of the SiS 471 chipset can help me in decoding what all this stuff means? 😁
Thanks!