Looks promising ... L1 data throughput is already ~4mb/s higher than on my board.
What do CHKCPU and CTCM say?

I've checked the AM486DX4 which came with the board on another BIOS - turns out it works and has 8kb WB cache (tested on the HOT 419 a friend of mine owns). Sadly I can't get it to work on the M912 ... no matter what the VCore always ends up at 2.35V instead of the intended 3.3V (tried the internal regulator and feeding it to the CPU externally).

cyclone3d wrote on 2020-10-01, 20:52:

AHAHAHAHAHAHAHAHA. This is rich. […]
Show full quote

AHAHAHAHAHAHAHAHA. This is rich.

Cachecheck v4 is not detecting the L1 cache at all with it set to enabled in the BIOS:
BIOS-L1_cache_set_to_enabled.jpg

I decided to try setting it to disabled in the BIOS and now it is picking it up and doing the L1 cache check. Before it was saying there was only 1 cache and that the first megabyte wasn't being cached.
BIOS-L1_cache_set_to_disabled.jpg

Have you set cache/ram timings, wait states, etc. in the BIOS and disabled autoconfig?
Your "memory access block sizes" timings are about 9 us/KB for L1, 29 for L2, and 55 for RAM. For comparison, I'm getting around 7, in the teens, and in the twenties on my 5x86-160 depending on whether I set cache to 3-2-2-2 (which seems necessary for two SIMMs at 40 MHz) or 2-1-1-1 (ok at 40 but with only one ram simm).

Pulled an EEPROM out of a probably dead AST 486 board.. backed up the contents and then flashed the combined image that is on vogonsdrivers.

The AMI, which is the first) doesn't POST, but the AWARD one did and so I ran a cachecheck bench with it.

The L1 cache shows up as expected and the main memory throughput is a lot faster than with the AMI.

The AWARD BIOS still detects the 8GB CF card as 1667MB though.. .so that is a BUMMER.

Going to try that 2Mb EEPROM again and see if it also works with the AWARD BIOS.. If so, I'll see if I can get a working combined image.

jakethompson1 wrote on 2020-10-01, 22:27:

cyclone3d wrote on 2020-10-01, 20:52:

AHAHAHAHAHAHAHAHA. This is rich. […]
Show full quote

AHAHAHAHAHAHAHAHA. This is rich.

Cachecheck v4 is not detecting the L1 cache at all with it set to enabled in the BIOS:
BIOS-L1_cache_set_to_enabled.jpg

I decided to try setting it to disabled in the BIOS and now it is picking it up and doing the L1 cache check. Before it was saying there was only 1 cache and that the first megabyte wasn't being cached.
BIOS-L1_cache_set_to_disabled.jpg

Have you set cache/ram timings, wait states, etc. in the BIOS and disabled autoconfig?
Your "memory access block sizes" timings are about 9 us/KB for L1, 29 for L2, and 55 for RAM. For comparison, I'm getting around 7, in the teens, and in the twenties on my 5x86-160 depending on whether I set cache to 3-2-2-2 (which seems necessary for two SIMMs at 40 MHz) or 2-1-1-1 (ok at 40 but with only one ram simm).

I haven't messed with any timings yet.. just testing with default settings for now.

2Mb EEPROM didn't work.

Also can't get the AMI BIOS to POST with the combined BIOS.

Even tried making a new combined BIOS, with having AMI and then AWARD.

Going to try the AMI BIOS by itself. IF that doesn't work, I am going to try backing up and burning the AMI BIOS I have and see if it works.

The AMI BIOS that is listed as 12-01 is really 7-25-1994.

Since that one has the date the same in both places, I would like to get it to POST so I can see if they fixed the cache enable/disable issue that mine has.

cyclone3d wrote on 2020-10-01, 23:41:

2Mb EEPROM didn't work. […]
Show full quote

2Mb EEPROM didn't work.

Also can't get the AMI BIOS to POST with the combined BIOS.

Even tried making a new combined BIOS, with having AMI and then AWARD.

Going to try the AMI BIOS by itself. IF that doesn't work, I am going to try backing up and burning the AMI BIOS I have and see if it works.

The AMI BIOS that is listed as 12-01 is really 7-25-1994.

Since that one has the date the same in both places, I would like to get it to POST so I can see if they fixed the cache enable/disable issue that mine has.

If you are trying the bios I uploaded here Re: PC Chips M912 BIOS update for Am5x86 and Cyrix 5x86 it really does print 12/01/95 when it boots up. I believe the issue is that 07/25/94 is the date that AMI delivered it to PC Chips, and 12/01/95 is the date that PC Chips used the elusive AMIBCP to build the bios image.

I've also been experimenting with write-back L1 cache on UM498 boards. From what I can tell the Write-Back option tells the chipset that the CPU is write-back. I'm not sure whether it actually changes the configuration of the CPU, which I believe determines whether to be write-through or write-back based on the WB/WT# signal at reset, which should be determined using jumpers only as that's too early for the bios to do anything.

Try using DOS DEBUG and input the following commands
o 28 a0
o 28 05
o 28 0a
i 2a

I believe you will find this outputs 40 if the BIOS option is set to L1 write-back and to 00 if it's set to write-through.
I'll have more on that later.

Managed to get the DX4 working (tested it in a friend's HOT419, where it's detected as a version with 8KB L1 Cache) - albeit as a DX2 at 66Mhz, writeback works and really instable.
Aww man. This board is really starting to annoy me. Does anyone of you have a printed original manual?

EDIT: @jakethompson1 getting "40" regardless of the setting (that's with the PODP5V83), testing the AM486DX4 later.

shock__ wrote on 2020-10-02, 00:17:

Managed to get the DX4 working (tested it in a friend's HOT419, where it's detected as a version with 8KB L1 Cache) - albeit as a DX2 at 66Mhz, writeback works and really instable.
Aww man. This board is really starting to annoy me. Does anyone of you have a printed original manual?

EDIT: @jakethompson1 getting "40" regardless of the setting (that's with the PODP5V83), testing the AM486DX4 later.

I have the printed manual for 1.4 but the person who I got the 1.7 board from apparently replaced a 1.4 board with this 1.7 board.

There are a bunch of notes in the manual and there is another insert for jumper settings which match what is on the 1.7 jumper page.

jakethompson1 wrote on 2020-10-01, 23:54:

If you are trying the bios I uploaded here Re: PC Chips M912 BIOS update for Am5x86 and Cyrix 5x86 it really does print 12/01/95 […]
Show full quote

cyclone3d wrote on 2020-10-01, 23:41:

2Mb EEPROM didn't work. […]
Show full quote

2Mb EEPROM didn't work.

Also can't get the AMI BIOS to POST with the combined BIOS.

Even tried making a new combined BIOS, with having AMI and then AWARD.

Going to try the AMI BIOS by itself. IF that doesn't work, I am going to try backing up and burning the AMI BIOS I have and see if it works.

The AMI BIOS that is listed as 12-01 is really 7-25-1994.

Since that one has the date the same in both places, I would like to get it to POST so I can see if they fixed the cache enable/disable issue that mine has.

If you are trying the bios I uploaded here Re: PC Chips M912 BIOS update for Am5x86 and Cyrix 5x86 it really does print 12/01/95 when it boots up. I believe the issue is that 07/25/94 is the date that AMI delivered it to PC Chips, and 12/01/95 is the date that PC Chips used the elusive AMIBCP to build the bios image.

I've also been experimenting with write-back L1 cache on UM498 boards. From what I can tell the Write-Back option tells the chipset that the CPU is write-back. I'm not sure whether it actually changes the configuration of the CPU, which I believe determines whether to be write-through or write-back based on the WB/WT# signal at reset, which should be determined using jumpers only as that's too early for the bios to do anything.

Try using DOS DEBUG and input the following commands
o 28 a0
o 28 05
o 28 0a
i 2a

I believe you will find this outputs 40 if the BIOS option is set to L1 write-back and to 00 if it's set to write-through.
I'll have more on that later.

Ok, cool. The problem I am having is that I can't get the AMI BIOS working with a 1MB EEPROM.. in either position.

I tried backing up and burning my copy as well and still can't get it to POST.

The AWARD BIOS work in either position when burned onto the 1MB EEPROM. Not sure if I am doing something wrong or if the AMI BIOS just won't work with the EEPROM I am trying to use or what.

Makes no sense as I would guess the combined image on vogonsdrivers would have been tested before uploading.

Found the html manual for the DX-6900 (M912) on the archived Amptron page. Also found the diagram.
http://web.archive.org/web/19970327140521/htt … om/manuals.html

Nothing new in them but nice to have I guess.

The 1.7 I pulled the newer AMI BIOS out of has a genuine looking UMC chipset, while the one I am using now has the PC-Chips sticker over the generic chipset.

I wonder if the real UMC chipset works with this BIOS properly as far as the L1 cache settings go.

I don't really see anything wrong with that board except for a bit of dirt so I think I am going to go ahead and try swapping stuff around to see if it actually works properly.... That L1 cache setting being backwards in that BIOS when used on this motherboard is just really strange.

I also wonder if the AMI BIOS will work on the DUAL BIOS setup on that other 1.7.

Anyway, here are the cachechk results with the AMI BIOS out of that other 1.7 set to fastest settings:

Tried the debug command on the latest Award BIOS and it returned 00 with it set to Write-Back.

Same for when it is set to Write-Through.

This Jan '96 1.7 really hates the older Award BIOS that came on my April '95 1.7 board. L1 and L2 cache are super sketchy about working... Set the L1 to Write-Back and the L1 completely goes away. Set the L2 to other than default timings and it goes away.

The AMI BIOS that came on the Jan '96 board has the same L1 bug where it has to be set to disabled for it to be enabled.

Running debug with the AMI BIOS that came with the Jan '96 board:
Settings in BIOS:
L1 Enabled
Write-Back
Result - 40
cachechk does not see L1 cache and results seems to indicate it is disabled

L1 Enabled
Write-Through
Result - 40
cachechk does not see L1 cache and results seems to indicate it is disabled

L1 Disabled
Write-Back
Result - 20
cachechk sees L1 cache and results seems to indicate it is enabled

L1 Disabled
Write-Through
Result - 20
cachechk sees L1 cache and results seems to indicate it is enabled

Some something is definitely screwy with either the BIOS or the chipset... My guess is the BIOS.

I still can't get the supposedly newer AMI BIOS to work even with this newer board when using the 1Mb EEPROM.

I guess the instable operation with the DX4 is due to the 3.3V mode severely undervolting at 2.4V (no matter whether I use the onboard regulator or feed 3.3V externally). Guess I'll have to check the board again.
I guess I'll downgrade to an earlier AMI BIOS to reproduce cyclone's results with the POD for now.

Looks like Neither Mouser or Digikey sell DIP28 512kb EEPROMs anymore. Went ahead and ordered 20 Winbond branded ones for a whopping $10 from China. Was hoping to find some cheaply in the US, but looks like nobody even sells them.

cyclone3d wrote on 2020-10-02, 20:48:

Looks like Neither Mouser or Digikey sell DIP28 512kb EEPROMs anymore. Went ahead and ordered 20 Winbond branded ones for a whopping $10 from China. Was hoping to find some cheaply in the US, but looks like nobody even sells them.

They do sell them as EPROMs (can only write once)

jakethompson1 wrote on 2020-10-03, 00:32:

cyclone3d wrote on 2020-10-02, 20:48:

Looks like Neither Mouser or Digikey sell DIP28 512kb EEPROMs anymore. Went ahead and ordered 20 Winbond branded ones for a whopping $10 from China. Was hoping to find some cheaply in the US, but looks like nobody even sells them.

They do sell them as EPROMs (can only write once)

Yeah, I saw those and didn't want to get them.

cyclone3d wrote on 2020-10-03, 01:13:

jakethompson1 wrote on 2020-10-03, 00:32:

cyclone3d wrote on 2020-10-02, 20:48:

Looks like Neither Mouser or Digikey sell DIP28 512kb EEPROMs anymore. Went ahead and ordered 20 Winbond branded ones for a whopping $10 from China. Was hoping to find some cheaply in the US, but looks like nobody even sells them.

They do sell them as EPROMs (can only write once)

Yeah, I saw those and didn't want to get them.

Ah. I'm not sure how much longer they will have them. The most recent 1024K, 32-pin EEPROMs I ordered from DigiKey came with a 2008 date code...

Turns out the 3.3V generation on my board is severely broken. Removed the transistor and shunt so I can at least feed in the 3.3V externally without the voltage dropping.
DX4 with WB works nicely.

shock__ wrote on 2020-10-03, 22:08:

Turns out the 3.3V generation on my board is severely broken. Removed the transistor and shunt so I can at least feed in the 3.3V externally without the voltage dropping.
DX4 with WB works nicely.

So it's just the Pentium OverDrive where WB is broken?

Correct.

EDIT: Just briefly reconfirmed this - same jumper settings as with the DX4 (funnily enough write-back gets disabled in the BIOS when jumpering the CPU to an "ordinary" DX4 [or DX2 @ 3.3V]), write-back can still be selected in the BIOS, but CTCM/CHKCPU stick with detecting the L1 scheme as write through.

shock__ wrote on 2020-10-03, 22:59:

Correct.

EDIT: Just briefly reconfirmed this - same jumper settings as with the DX4 (funnily enough write-back gets disabled in the BIOS when jumpering the CPU to an "ordinary" DX4 [or DX2 @ 3.3V]), write-back can still be selected in the BIOS, but CTCM/CHKCPU stick with detecting the L1 scheme as write through.

Yeah. I'm thinking whether the CPU is actually write-back or not is determined entirely by jumpers, and the bios/chipset settings are just controlling whether the chipset is to look out for the HITM signal or not (which tells hardware that does DMA e.g. the floppy controller -- hold on a second I've got dirty data in L1 that better be flushed before you read from RAM) and as I've observed, can also control whether the chipset electrically blocks the A20 line from the cpu when it is disabled, or just sets the A20M signal and trusts the cpu to do the right thing.