feipoa wrote on 2020-04-17, 09:59:

Motherboard is a Daewoo AL486V-D, aka Panda 386V. SXL2-50 running at 2x25 MHz with Cyrix FasMath CX-83D87 […]
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Motherboard is a Daewoo AL486V-D, aka Panda 386V.
SXL2-50 running at 2x25 MHz with Cyrix FasMath CX-83D87

See comments in the photos.

SXL2-HWiNFO32_1.jpg
SXL2-HWiNFO32_2.jpg
SXL2-HWiNFO32_3.jpg
SXL2-HWiNFO32_4.jpg
SXL2-W95.LOG

Thanks! Could you please create and upload the HWiNFO32 Debug File? Here's how to do it in case you haven't done yet: https://www.hwinfo.com/forum/threads/read-thi … g-a-report.241/

Regarding the co-proc, AFAIR there were 2 versions of 83D87/83S87: "Old" and "New", but I really don't recall why/what was the difference, I just have code to detect the difference 😁

I mentioned it in the CPU-Z thread.

Configuration Control Register 0 (aka, CCR0) bit 6 If it is set high (1) that means the 2x multiplier is active, if set low (0) the CPU is in 1x mode.

Should be that the Cyrix did something to the newer FasMath chips to make them more compatible with DLC chips, but this update slowed the FPU down ever so slightly. Usually the grey-tops are marginally faster than the blacktops, but I maybe some newer grey-tops are also the updated version - I'm not sure.

I'm trying to get an ethernet card on my test bed to avoid the floppy swap, so haven't got to the debug file yet. I'm also trying to do cpu-z's testing at the same time. I also had set some timings too aggressively in the BIOS which had corrupted my hard drive and I had to restore it. So I'm a bit slow this evening.

OK. Got networking going. Here's the report and debug for the SXL2-50 system.

Thanks. If it's not a big problem, could you please try to read Cyrix config register C4h, C7h, CAh, CDh there? I'm wondering what values this gives here... The should be N/A on TI486SXLC but available on TI486SXL (and TI486SXL2 probably too).

Read those registers with what? Any particular software or debug command I should know about?

feipoa wrote on 2020-04-17, 10:46:

Read those registers with what? Any particular software or debug command I should know about?

I thought you have some tool for that 😀 No problem, I will read them and put the content into DBG of new build 😀 Just a minute 😉

Here a new test build, should fix and improve some things there: www.hwinfo.com/beta/hwi32_625_4139.zip

I do for the Cyrix 5x86, but the register program for the SXL that I use is more limited.

Let me see if CTCHIP34 works with SXL chips.

These are the registers that CTCHIP34 can read for DLC/SXL chips. Looks like it has what you need.

1;********** Cyrix/Texas 486SLC/DLC in CX486.CFG********************
2
3INDEXPORT=22h
4DATENPORT=23h
5
6FLUSH=INVD
7
8INDEX=C0h; Configuration Control Register 0
9
10BIT=7    ;0/1 (Suspend) /SUSP input and /SUPSA output
11BIT=6    ;    (CO)     Cache-Organisation
12                 0= 2-Way
13                 1= direct mapped
14BIT=5   ;0/1 (BARB)   Flush Cache every HOLD
15BIT=4   ;0/1 (FLUSH)  /Flush input pin (DLC:E13, SLC:30)
16BIT=3   ;0/1 (KEN)    /KEN  input pin  (DLC:B12, SLC:29)
17BIT=2   ;0/1 (A20M)   /A20M input pin  (DLC:F13, SLC:31)
18BIT=1   ;0/1 (MC1) 640K-1M non-cacheable
19        ;                               (Bug in A4/A5 Stepping!)
20BIT=0   ;0/1 (NC0) First 64KB always not cacheable
21        ;                               (Real/Virtuell)
22
23INDEX=C1h; Configuration Control Register 1
24Bit=0   ; 0/1 (RPL)  output pins /RPLSET and /RPLVAL
25
26INDEX=C4h; Non Cacheable Region Register (Default=00h);
27BIT=7654321      ; A31 - A24 of starting address Region 1
28
29INDEX=C5h; Non Cacheable Region Register (Default=0Ah);
30BIT=76543210     ; A23 - A16 of starting address Region 1
31
32INDEX=C6h; Non Cacheable Region Register (Default=06h);
33BIT 7654         ; A15 - A12 of starting address Region 1
34BIT=3210         ; Size of non-cacheable Region 1
35
36INDEX=C7h; Non Cacheable Region Register (Default=00h);
37BIT=7654321      ; A31 - A24 of starting address Region 2
38
39INDEX=C8h; Non Cacheable Region Register (Default=0Ah);
40BIT=76543210     ; A23 - A16 of starting address Region 2
41
42INDEX=C9h; Non Cacheable Region Register (Default=06h);
43BIT 7654         ; A15 - A12 of starting address Region 2
44BIT=3210         ; Size of non-cacheable Region 2
45
46INDEX=CAh; Non Cacheable Region Register (Default=00h);
47BIT=7654321      ; A31 - A24 of starting address Region 3
48
49INDEX=CBh; Non Cacheable Region Register (Default=0Ah);
50BIT=76543210     ; A23 - A16 of starting address Region 3
51
52INDEX=CCh; Non Cacheable Region Register (Default=06h);
53BIT 7654         ; A15 - A12 of starting address Region 3
54BIT=3210         ; Size of non-cacheable Region 3
55
56INDEX=CDh; Non Cacheable Region Register (Default=00h);
57BIT=7654321      ; A31 - A24 of starting address Region 4
58
59INDEX=CEh; Non Cacheable Region Register (Default=0Ah);
60BIT=76543210     ; A23 - A16 of starting address Region 4

61
62INDEX=CFh; Non Cacheable Region Register (Default=06h);
63BIT 7654         ; A15 - A12 of starting address Region 4
64BIT=3210         ; Size of non-cacheable Region 4

Mumak wrote on 2020-04-17, 10:55:

Here a new test build, should fix and improve some things there: www.hwinfo.com/beta/hwi32_625_4139.zip

attached

Mumak wrote on 2020-04-17, 10:39:

could you please try to read Cyrix config register C4h, C7h, CAh, CDh there? I'm wondering what values this gives here... The should be N/A on TI486SXLC but available on TI486SXL (and TI486SXL2 probably too).

C4h = 00000000
C7h = 00000000
CAh = 11000000
CDh = 00000000

Thanks. Here a new build that should fix the clock ratio and cache reporting: www.hwinfo.com/beta/hwi32_625_4140.zip
Btw, is Potomac the codename or part of the official name?

I'm pretty sure it was a code name for the SXL chip series. Perhaps named after the street name for TI's Colorado sales office?

COLORADO: Aurora: 1400 S. Potomac Street,
Suite 101, Aurora, CO 80012, (303) 368-8000.

Here's the latest debug and report.

Still contains PnP entries, like the ESS sound card, which are non-existent on the testbed. CPU multiplier and FSB are correct now.

EDIT: I figured I should warn you what my next move is - as with CPU-Z, to ensure it shows L1 disabled when L1 is disabled. Some motherboards have it disabled by default, so it would be nice to know when it is on or off. If you are planning on being able to determine if the L1 cache is enabled or disabled, you'll need to read CR0 bit 30. 1=L1 disabled; 0=L1 enabled. Note that CR0 !=CCR0.

feipoa wrote on 2020-04-17, 13:06:

Here's the latest debug and report.

Still contains PnP entries, like the ESS sound card, which are non-existent on the testbed. CPU multiplier and FSB are correct now.

EDIT: I figured I should warn you what my next move is - as with CPU-Z, to ensure it shows L1 disabled when L1 is disabled. Some motherboards have it disabled by default, so it would be nice to know when it is on or off. If you are planning on being able to determine if the L1 cache is enabled or disabled, you'll need to read CR0 bit 30. 1=L1 disabled; 0=L1 enabled. Note that CR0 !=CCR0.

Thanks. I will need a registry dump of the HKEY_LOCAL_MACHINE key to determine how to skip the entries no longer present.

Here's the debug file for the SXL2-66 system in Win95c (AMI Mark V Baby Screamer motherboard). System creased with a BSOD during analysing hardware.

1A fatal exception 0D has occured at 0028:C0004357 in VXD VMM(01)03357.

Do you know which SIO chip is there, perhaps some National Semiconductor (NS) ?

Chips & Technology, isn't it? http://mail.lipsia.de/~enigma/neu/pics/386babyscreamer.jpg

I'd have to remove the case to get the exact part number.

And here a new build to fix the crash during LPC check: www.hwinfo.com/beta/hwi32_625_4141.zip
This should also fix reporting of PnP device no longer present in system, but I think you have already archived that board.

The Panda board is still out on the testbed - I have two testing areas. I'll check it this evening.