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Xi 8088 by Segey Kiselev

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Reply 300 of 613, by keenerb

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I fired off an email to James Pearce about the lo-tech memory board; I'm not sure it was intended to COMPLETELY replace on-board memory, or if that's even possible.

I wouldn't think that the xi8088 bios would have any special checks for on-board vs. on-bus memory in bios startup.

Sergey did mention using a separate memory board rather than the on-board memory. I wonder if disabling the chip enable lines on the while leaving everything else connected could have any impact; I could pop out the memory chip, straighten out that leg, and re-insert.

Another thing that's curious (to me) is that A19 is connected directly to CE on chip 1, but A19 is filtered through a lot of logic on "Memory Chip Select" side. On the lo-tech board, both chips have their own select logic. Is there any chance both chip 1 and 2 could have CE enabled at the same time, or that the delay the additional logic introduces on chip 2 causes data to be retrieved from chip 1 instead, because it responded first? It may be that the select logic only sets CE low on U12 when CE is high on U11, and vice-versa, I can't really tell for sure reading the schematic.

I noted previously that simple memory errors were obvious fairly frequently where : would be ! in a batch file.

:start
xdir
goto start

This simple test inevitably fails. I'd get the error that it couldn't find the label "!start" after X repetitions, but of course it wasn't always !start, it might be "$dir command not found" or "goto stert", but one character (or more) would eventually be wrong.

Last edited by keenerb on 2017-05-05, 17:06. Edited 1 time in total.

Reply 301 of 613, by BloodyCactus

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the lotech 1mb board is designed to replace low memory. I dont know about the 2mb board tho.

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Reply 303 of 613, by keenerb

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I also have a Boca 384k memory expansion board and two Intel Aboveboard 286 cards that supposedly can back-fill system memory, but I'm not 100% sure if they can backfill ALL system memory...

Reply 304 of 613, by smbaker

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keenerb wrote:

I wonder if disabling the chip enable lines on the while leaving everything else connected could have any impact; I could pop out the memory chip, straighten out that leg, and re-insert.

Why not remove the whole chip? Leaving the chip select line floating may cause trouble.

Just to clarify, when you add the Lo-Tech board and use it for the lower 512K, you are removing the lower SRAM chip from the Xi 8088, right?

keenerb wrote:

Another thing that's curious (to me) is that A19 is connected directly to CE on chip 1, but A19 is filtered through a lot of logic on "Memory Chip Select" side.

I would assume that A19 is the address bit that selects between the lower 512K and the upper 512K. For the Xi 8088, it's assumed that you always want to map the entire lower 512K, so one line can enable the lower SRAM chip. For the upper 512K, or for the Lo-Tech board, there is the provision to select different portions of the address ranges, so there's more logic.

keenerb wrote:

Is there any chance both chip 1 and 2 could have CE enabled at the same time, or that the delay the additional logic introduces on chip 2 causes data to be retrieved from chip 1 instead, because it responded first? It may be that the select logic only sets CE low on U12 when CE is high on U11, and vice-versa, I can't really tell for sure reading the schematic.

I did try removing the upper SRAM from my Xi 8088. It's perfectly happy booting with only 512K of RAM (you should do this to see if it affects your stability). In my case, the stability problems persisted even with the upper SRAM removed. So I don't think it's the case that the two chips are being selected at the same time.

Reply 305 of 613, by keenerb

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I believe there is some sort of incompatibility with lotech board and xi8088. I get system memory failure beeps with only lotech, and any combination of lotech board and main memory results in xi only reorting 64k, and no memory error.

Reply 306 of 613, by BloodyCactus

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Yellow is D0, Blue is A0...

notice each time A0 rises or falls, there is a blip at the EXACT same time on the D0 line...

every rise + fall on A0 shows a bounce on D0.. I guess I am and am not surprised. Both A0 + D0 go though 74F245 bus tranceivers...

6N4yR73.png

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Reply 307 of 613, by BloodyCactus

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interestingly, while I had the scope in run mode the system locked up, memory/data addresses kept running. so the cpu isnt locked up, but keyboard + display was.

also while on the scope, with A0, system would not boot properly.. detach a0, fired right up. I find that interesting.

--/\-[ Stu : Bloody Cactus :: [ https://bloodycactus.com :: http://kråketær.com ]-/\--

Reply 308 of 613, by smbaker

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Am I reading this right that you're only getting about a 400mv swing on A0 and a 550mv swing on D0? If I recall correctly, I'm getting approximately a 5V swing. Any chance your probe is switched to X10 but setup as X1 in your scope? This seems odd that we're getting such differences in signal voltages between your setup and mine.

I suspect the D0 bumps you're seeing are when the data bus is in high impedance state, for whatever that's worth. Particularly in the vicinity of low bits, you can see where the data bus is going into high-impedance and starting to drift, and the address bit changes right in the middle of that (which makes sense; addressing should be changing while there's no data actively in flight).

In my case, whenever I experience a lockup, it's accompanied by no more MEMR signals, as that's the one I was triggering off of. The clock continues running. I haven't checked to see whether anything is happening on the address or data buses, but I'll be sure to pay more attention next time.

Some more anecdotal results from my experiment -- it's been running memory tests for about four hours with 7 cards and my bus terminator installed. No memory errors. Without the bus terminator installed, I typically get around 20 to 30 minutes in the 7-card configuration. EDIT: I jinxed it by writing that. It just registered a memory error. Still, it's much more stable with the terminator than without.

Reply 309 of 613, by carlostex

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keenerb wrote:

I believe there is some sort of incompatibility with lotech board and xi8088. I get system memory failure beeps with only lotech, and any combination of lotech board and main memory results in xi only reorting 64k, and no memory error.

It could be, all the lo tech 1MB RAM boards i've assembled, for myself and for sale, have worked fine, and can replace low memory indeed.

Reply 310 of 613, by BloodyCactus

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yes I was in x10 from another project I was working on.

anyway, back to x1, here is an oddity I hit;

U9YFBiq.png

Now, I wonder, if all the lines go high at the same time, if it magnifies the blip when a single line goes high. Something caused both lines to go beyond thier normal high.

Ill do some probing of MEMR,ALE,AEN etc later today.

--/\-[ Stu : Bloody Cactus :: [ https://bloodycactus.com :: http://kråketær.com ]-/\--

Reply 311 of 613, by keenerb

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I think I have problems with my 1mb board. Some of the 10k resistor arrays are giving strange readings, possibly I overheated them and damaged them. One reports 19.24M ohms resistance across, which seems a little excessive...

Reply 312 of 613, by smbaker

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keenerb wrote:

I think I have problems with my 1mb board. Some of the 10k resistor arrays are giving strange readings, possibly I overheated them and damaged them. One reports 19.24M ohms resistance across, which seems a little excessive...

I was going to suggest taking a look at that. The symptoms (conflicts with Xi 8088 RAM regardless of switch settings, inability to backfill and replace Xi 8088 RAM, etc) sounded like maybe something may be wrong with the pullups.

I'm continuing to have positive results from my terminator experiments. My latest attempt is an active terminator, 330 ohm resistors from each bus pin to a regulated 2.7 V supply.

I also designed a breakout board to adapt 36-pin J-lead SMD memory (AS7C4096, CY7C1049, etc) to the AS6C4008 footprint. I'm not sure whether I'll bother trying this, but the breakout board was pretty easy to design and cheap to make. These are 10ns RAM chips, for what it's worth.

Reply 313 of 613, by keenerb

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I don't think it's my 1mb card. Replaced the resistor arrays and it's still misbehaving in xi8088, but has always worked fine in various Tandy machines. I feel like the xi8088 is still trying to decode and respond to the memory requests.

Last edited by keenerb on 2017-05-08, 14:25. Edited 2 times in total.

Reply 314 of 613, by keenerb

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smbaker wrote:
I was going to suggest taking a look at that. The symptoms (conflicts with Xi 8088 RAM regardless of switch settings, inability […]
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keenerb wrote:

I think I have problems with my 1mb board. Some of the 10k resistor arrays are giving strange readings, possibly I overheated them and damaged them. One reports 19.24M ohms resistance across, which seems a little excessive...

I was going to suggest taking a look at that. The symptoms (conflicts with Xi 8088 RAM regardless of switch settings, inability to backfill and replace Xi 8088 RAM, etc) sounded like maybe something may be wrong with the pullups.

I'm continuing to have positive results from my terminator experiments. My latest attempt is an active terminator, 330 ohm resistors from each bus pin to a regulated 2.7 V supply.

I also designed a breakout board to adapt 36-pin J-lead SMD memory (AS7C4096, CY7C1049, etc) to the AS6C4008 footprint. I'm not sure whether I'll bother trying this, but the breakout board was pretty easy to design and cheap to make. These are 10ns RAM chips, for what it's worth.

What would it take to include a buffer on that breakout board? James Pearce's card has a buffer, the schematic is here:

https://www.lo-tech.co.uk/w/images/a/a2/Lo-te … hematic-r02.png

I feel like each breakout board would require it's own 74ACT245 but otherwise use the signalling that's already available on the socket.

Reply 315 of 613, by smbaker

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keenerb wrote:

What would it take to include a buffer on that breakout board? James Pearce's card has a buffer, the schematic is here:

Space is pretty tight, since I made the board approximately the size of an AS6C4008 chip. Maybe one could try to fit the buffer on the underside of the board. I'll play with the layout and see if there's a way.

Scott

Reply 317 of 613, by smbaker

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I made the buffer fit:

memadapt-buffered.jpg
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I did have to violate the design rules for osh park to make it happen though (calls for 15mil board edge-to-trace clearance; I reduced it to 10mil, which will probably work). I'll sanity check this some more tonight and then see about getting some prototypes made.

Reply 318 of 613, by keenerb

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If you order a couple I'll reimburse you for two, if you want to make a big batch.

Assuming you're U.S. based, anyway. Obviously they are untested and possibly (likely?) not going to work, but the more the merrier when it comes to troubleshooting.