feipoa wrote:

In cases whereby one motherboard shows a marked improvement when using SDRAM over EDO, it would be very interesting to compare such a board with another of an identical chipset which did not show improvement when using SDRAM. It is possible that the board which you suspect is dodgy may just be able to run its EDO as fast as the board which shows a marked improvement when using SDRAM. It could also be a dodgy board. I don't know, but there isn't enough testing to make such determinations.

Pretty sure these boards were up to scratch - in absolute figures the values I got for i430TX with SDRAM were the third best of any So7 motherboard/chipset (only the ALi Aladdin IV+ and V were faster, clock for clock), and the values for both TX boards were almost identical for SDRAM. It was the EDO performance that differed between the two.

Unfortunately I don't have the boards any more, so can't go any deeper into it now.

How did I come up with this theory? I noticed that on some 486 boards which properly support EDO RAM and do show improvement when using EDO over FPM, those boards did not outperform other 486 boards with FPM RAM.

There's support and support... early EDO implementations worked, but were probably less optimized than pure FP. Same thing happened with EDO vs SDRAM: i430HX with pure EDO was about as fast as i430VX with SDRAM and a lot faster than the VX with EDO.

I will get deeper into this - it has been on my list for some time. I own at least one board for each Intel Pentium chipset from socket 4 to socket 7. I'll also throw the MVP3 and ALi Socket 7 in there, but my focus was to see how performance improved from one chipset to the next, while maintaining the CPU freq. constant. I will vary the RAM type as per our discussion. I have no idea when I will have time to run this...

Great! That's what I used to have, before I was forced to offload it all when I moved to a tiny apartment in the big city.
I did the same, benching everything with a P100 at 66MHz FSB (the one speed every board could do)

Here's the raw data I still have:
http://dionb.eu/chipset1.html

Did you create a chart or graph?

I think I'll need to use 133 MHz because Socket 4 is either 60, 66, or 133 MHz POD. Or will the POD drop to 100 MHz with the fan removed? If it does, that would be even better so I don't have to use a socket 5 upgrade module for the other boards.

feipoa wrote:

Did you create a chart or graph?

Nope, just the raw data.

I think I'll need to use 133 MHz because Socket 4 is either 60, 66, or 133 MHz POD. Or will the POD drop to 100 MHz with the fan removed? If it does, that would be even better so I don't have to use a socket 5 upgrade module for the other boards.

Never played around with the POD, so don't know. Worth trying though, as the So3 PODP certainly does drop the multiplier like that. Problem with 133MHz is that many early So5 boards (particularly the OEM ones) only had a fixed 1.5x multiplier, no 2x.

Yeah, that's why I'd need to use an upgrade interposer module to set the multiplier.

If I recall the idea was that EDO without L2 was about as quick as FPM with L2, when they were dropping L2 to cut costs

I haven't heard that. Seems unlikely, but perhaps some chipset implementations make this possible? Another something to add to the list.

Back in the day it made quite the difference I guess.
Nowadays, if it's a SSocket 7 board, one can just insert a K6-2+ or -III+ and still have the board roar.
I used to run an older M5ATA without cache, due to IC failure, and it was still a good performer - way better than the i430TX based ones for example.

A 486 is pretty dire and the only thing that may improve a bit is the mem-/write speed when going from Writeback to "Bareback".

Matth79 wrote:

If I recall the idea was that EDO without L2 was about as quick as FPM with L2, when they were dropping L2 to cut costs

Before putting away my 430HX motherboard, I decided to test this theory using Quake's timedemo in DOS with a K6-2 (no integrated cache) at 500 MHz (6x83.3). The results were:

EDO (with L2 cache): Quake = 44.4 fps
EDO (without L2 cache): Quake = 37.4 fps

FPM (with L2 cache): Quake = 43.4 fps
FPM (without L2 cache): Quake = 35.7 fps

So, it was quite a bit better (16%) to use FPM with L2 cache compared to using EDO without L2 cache. The benefit of using EDO (w/L2) over FPM (w/L2) was 2.3%, while the benefit of using EDO (w/out L2) over FPM (w/out L2) was 4.8%. For EDO systems, the benefit of L2 cache was an 18.7% performance boost, for FPM, it was 21.6%.

I wonder if SDRAM can approach the L2 cache speed on some chipset with the tightest settings

Deksor wrote:

I wonder if SDRAM can approach the L2 cache speed on some chipset with the tightest settings

not really in theory. no matter how fast a dram is, its principles of operation is inherently more complicated and slower than sram.
well... unless the cache controller is designed without common sense. i think ali5 makes such an example, its got superb sdram performance but unimpressive cache, enabling cache even causes a penalty on sdram performance(an issue which seemed common back in the 386 ages). as a result, there is only 1~2% difference in most benchmarks with or without oncoard cache. i think thats why the following ali7 chipset was designed without supporting any onboard cache.

feipoa wrote:

Before putting away my 430HX motherboard, I decided to test this theory using Quake's timedemo in DOS with a K6-2 (no integrated […]
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Matth79 wrote:

If I recall the idea was that EDO without L2 was about as quick as FPM with L2, when they were dropping L2 to cut costs

Before putting away my 430HX motherboard, I decided to test this theory using Quake's timedemo in DOS with a K6-2 (no integrated cache) at 500 MHz (6x83.3). The results were:

EDO (with L2 cache): Quake = 44.4 fps
EDO (without L2 cache): Quake = 37.4 fps

FPM (with L2 cache): Quake = 43.4 fps
FPM (without L2 cache): Quake = 35.7 fps

So, it was quite a bit better (16%) to use FPM with L2 cache compared to using EDO without L2 cache. The benefit of using EDO (w/L2) over FPM (w/L2) was 2.3%, while the benefit of using EDO (w/out L2) over FPM (w/out L2) was 4.8%. For EDO systems, the benefit of L2 cache was an 18.7% performance boost, for FPM, it was 21.6%.

HX board? Sounds like PLB. Almost certainly that theory dates to the asynch cache era, when the difference would have been much smaller. This would be something to test on an i430FX or SIS 5(5)01 board with asynch. Now, I just happen to have an So4 SiS 501 board with asynch cache... unfortunately no time tonight, but maybe tomorrow evening I'll be able to test it.