If the socket has 24 pins, you'd better try to get the 24 pin chip. I am pretty sure Cypress and Micron make one.
64kx4 should also work

http://m.ebay.com/itm/1x-MICRON-MT5C2564-15-6 … %257Ciid%253A15

Write back will probably make it slower due to the additional latency on writes compared to write through.
There will be a gain if the cache is a lot faster than memory, but that is not the case with a 386.
Even on a 486DX2-66 write through is in most cases faster than write back.

That doesn't seem at ends with what I've been reading, as most of the articles I read were from Pentium 90 machines and above. The 386 has (I think) 70NS, it could be 60NS RAM, and the cache is 20NS, whereas the 16x4 I was eyeing (and the suggested 64x4) are both 15NS.

It might be worth the experimentation - First thing's first, gotta get that tag chip off the board...

Thanks for the input thus far.

The rated speed of the cache and the rated speed of memory chips do not determine the speed of memory read/write or cache read/write to the system; it is controlled by wait states imposed by the system. Faster cache/RAM can handle reduced wait states, but there is a limit to how little they can be. If your system is already stable with the lowest wait state, then replacing the cache or RAM with faster memory will not speed up the system.

I think elianda's comment was speaking from his personal experimentation experience and noticing that using write-back L2 cache on 486 systems at speeds 66 MHz and slower yielded [slightly] worse benchmark performance. Even on an AMD Am5x86-133 or 160 system, using write-back L2 cache produced only small improvements in select benchmarks.

You can view the difference in 386 RAM and L2 cache speeds in this thread, Post your 386 Speedsys results here

What I don't understand is elianda's statement about there needing to be a large delta between RAM and cache for write-back (as opposed to write-through) L2 cache to make a difference. Are you implying that the delta increases with increasing CPU speed, e.g. DX4-100/133 vs. DX33? Wouldn't it be approximately the same?

Maybe he is referring to L1 cache as it runs at cpu speeds.

When dealing with older 386's/486's... the Front Side Bus (FSB) determines really how fast your system can run and what cache you need.

If you have an FSB of 33MHz... then 1/33,000,000 = 3.03 x10 to the power of -8 = a system timing of 30ns, = 30ns cache!
If you have an FSB of 40MHz... then 1/40,000,000 = 2.50 x10 to the power of -8 = a system timing of 25ns, = 25ns cache!

At 33MHz, with 70ns DRAM simms... cache will be 2.33 times faster
At 33MHz, with 60ns DRAM simms... cache will be 2.00 times faster!

At 40MHz, with 70ns DRAM simms... cache will be 2.80 times faster
At 40MHz, with 60ns DRAM simms... cache will be 2.40 times faster!

As you decrease latency, you need faster DRAM i.e. 50ns!

EDIT: - Sorry this was meant for another thread... but is in some way applicable here too, hence why I'll leave it here.

I seem to recall when calculating the speed of the cache, you need to factor in some extra time for the address decoding.

Anonymous Coward wrote:

I seem to recall when calculating the speed of the cache, you need to factor in some extra time for the address decoding.

I'm not sure about that... it may be with some IC's, you would need to check for the specific datasheet.

Generally, a full cycle is factored into the IC's rating i.e. for a 25ns cache IC... each instruction takes a portion of the 25ns... i.e. instruction 1 = 8ns (usually addressing), then instruction 2 = 5ns, instruction 3 = 8ns (usually the operation read/write)... and so on to accumulate a total of 25ns.

Just look in the later pages of an IC's datasheet... it breaks down the timings for each cycle for each IC.

386_junkie wrote:

When dealing with older 386's/486's... the Front Side Bus (FSB) determines really how fast your system can run and what cache you need.

If you have an FSB of 40MHz... then 1/40,000,000 = 2.50 x10 to the power of -8 = a system timing of 25ns, = 25ns cache!

At 40MHz, with 70ns DRAM simms... cache will be 2.80 times faster

Looks like I'm set up optimally then. 😁

More here:

a 386 with 256K cache? It is done and works, mostly (questions inside)

Jed118 wrote:

Looks like I'm set up optimally then. 😁

Maybe...

What is your DRAM rated at? 80, 70, 60, or 50ns?

At 25ns system speed... you'll need 4 clock cycles to accress 80ns DRAM, 3 cycles to access either 60ns or 70ns DRAM, but...

with 50ns DRAM, you'll only need 2 cycles!!! That would be really fast.

p.s. Great work with the solder job!

My DRAM is 70NS - I'm afraid that I have reached my wife's patience limits with spending on these old computers for now 😉 - I'm actually using up any spares I have to build a decent 386DX/40 in order to sell it - All I need now is a PSU and a video card.

Car tuning season has started, and I will already have to contend with expenses related to a new race clutch setup for an even older car than my 386 so 50NS RAM will have to wait 😁

The soldering is not too bad - I think I may have a cold solder somewhere where I had to use solid copper wire to emulate chip legs - The copper was a bit old and I had to clean it off to get it shiny, but the solder didn't really want to stick too well, hence the globbing near the last pins. I'm going to pick up a fresh 28PIN DIP socket just in case, try to find the 10th SRAM chip (I dropped it somewhere, whether at work or at home) and be ready to redo it if there is the slightest error.

tell your wife to stfu and do whatever you want with your money 😁