Being one of the guys who burned large number of expensive hardware by simply inserting things the wrong way, i would strongly suggest to have as many big glowing markings in as many places as possible.

feipoa wrote on 2022-12-14, 13:05:

rasz_pl, attached are the FFT results cropped to the periods of interest w/x10 probe. Expecting something at 60 Hz, 5 KHz, 40 MHz, and 80 MHz and this is pretty much what we get.

You said earlier you measure while sitting in dos prompt, try while running something CPU intensive in different graphic mode. Doom for example.

feipoa wrote on 2022-12-14, 13:05:

I ran the variable DC supply again with 1 metre shielded cables connected to the scope probe. I then moved the tip of the scope probe around the motherboard to see which component is generating the 5 KHz.

you mean just waving probe over the board without connecting to the board? Thats weird, I dont remember seeing it on 5V rail.

feipoa wrote on 2022-12-14, 13:05:

When I move the probe tip over the FPU, BIOS, UM82C206F, or UM82c482, I see the same 5 KHz waveform on the scope. Vpp increase with increasing distance to the component, e.g. from 100 mV to 175 mV. When I move the probe tip over the SXL2, 80 Mhz oscillator, or UM82C481 I do not see the waveform. Isn't there a crystal on these motherboards used to set the data/time which runs in the KHz range?

you could check what frequency 8253 channel 0 is set at (IRQ 0). Its generating DOS timer interrupt. https://wiki.osdev.org/Programmable_Interval_ … e_Current_Count

Sphere478 maybe this will convince you how useless that overengineered 5V plane is 😀 https://www.youtube.com/watch?v=kdCJxdR7L_I 'Do You Really Need Power Planes? Are you sure? | Eric Bogatin'

I keep trying to remind you it’s not about current carrying capability it’s about decreasing the resistance as much as possible so that we can have a stable of a voltage as possible. The thinner the wire the more the load spike.

Just look at the leads that feiopa had on his psu massive voltage drop but he could still hold the current

We want to avoid as much voltage drop as possible.

By the way I was able to massively improve the ground plane on this latest version it is really tightly tied together now

Sphere478 wrote on 2022-12-15, 19:52:

I keep trying to remind you it’s not about current carrying capability it’s about decreasing the resistance

grab multimeter and measure resistance of super long 1mm wide track

Sphere478 wrote on 2022-12-15, 19:52:

as much as possible so that we can have a stable of a voltage as possible. The thinner the wire the more the load spike.

impedance, and doesnt matter with another ldo and bunch of caps at the other end

Sphere478 wrote on 2022-12-15, 19:52:

Just look at the leads that feiopa had on his psu massive voltage drop but he could still hold the current
We want to avoid as much voltage drop as possible.

cable+connector must have had 2 ohms to produce that much drop while providing barely 200ma

Here is the mobo I wanna put this adapter in. Anything I should know?

(I know about the varta 🤣)

What is max ram? I can physically fit 128mb of ram in it, but I suspect it won’t work?

okay. I added triangles.

Time to order. 😀

rasz_pl wrote on 2022-12-15, 07:21:

You said earlier you measure while sitting in dos prompt, try while running something CPU intensive in different graphic mode. Doom for example.

Ran DOOM, but peak FFT values remained the same.

rasz_pl wrote on 2022-12-15, 07:21:

you mean just waving probe over the board without connecting to the board? Thats weird, I dont remember seeing it on 5V rail.

It was there I guess, just not so obvious with 100-200 mV per division. 50 mV /div with x10 prove shows there is something periodic at 5V. With standard x10 probe:

With low inductance probe x10:

rasz_pl wrote on 2022-12-15, 07:21:

you could check what frequency 8253 channel 0 is set at (IRQ 0). Its generating DOS timer interrupt. https://wiki.osdev.org/Programmable_Interval_ … e_Current_Count

Do you have a runable DOS executable? I tried to compile that with my old Borland C++ 5.5 after adding #include <stdio.h>, and int main(void), but the compiler complained of syntax errors. I haven't programmed/compiled with Borland in over 20 years, so I gave up immediately. :)

Something that I don't quite understand is the core frequency on 386 systems. The CPU's CLK2 pin shows 80 Mhz and matches the oscillator installed. I see no other frequencies on the scope on CLK2. In the CPU's 1x default mode, 40 MHz, looking at the frequencies observed on VCC3, we see that the 80 MHz freq. has twice the amplitude as the 40 Mhz freq, but the 40 Mhz freq. is still present. :

Where does it come from? Is it actually that all 386's simply half the incoming frequency with onboard PLL and run the system at this halved frequency? Or do regular 386 CPU's merely perform instructions on every other clock signal to make it 40 MHz equivalent, kind of the opposite of DDR memory?

In 2x mode, which is not the default mode on an SXL, we see that 40 MHz signal disappears and the 80 Mhz signal halves, but a 90 MHz signal of the same relative amplitude appears:
What's going on here?

I was also wondering if anyone had any other design suggestions for the PCB? Seems like it might be ready for a second round, assuming the price isn't ridiculous.

What got me thinking was the layers of PCB which don't have ground between them, meaning close signal traces creating cross-talk. I was wondering for these layers if the direction of the traces matters and could be optimised? For example, should the the traces on these planes always be parallel, anti-parallel, or perpendicular? If I recall correctly, when running ethernet cables behind walls and what not, when they cross your mains, they should always cross perpendicular to reduce the interference. I was wondering if such a circumstance would apply to this PCB?

I was also curious if sphere swapped the layers based on rasz's suggestion, or was that undertaking too involved? Or did you think it not beneficial?

I did swap layers.

Good call rasz

Yes perpendicular reduces cross talk.

I had meant to do it about 10 or so pages back 🤣 but had forgotten. Yes definitely a good call. The new model is better in every way it seems except:

- the signals now have more vias which was needed for the smaller footprint and the order of pins on the header (should be fine)

-current carrying capability of vcc3 and vcc5 plane is lower but still should be sufficient by themselves. But given that both the motherboard and cpu augment these planes with their own planes. We should be fine.

I didn't quite follow the outcome for perpendicular traces. Did you implement it already, are going to implement it, or are not going to implement it?

It has already been implemented. Layer swap.

feipoa wrote on 2022-12-16, 12:42:

It was there I guess, just not so obvious with 100-200 mV per division. 50 mV /div with x10 prove shows there is something periodic at 5V. With standard x10 probe

you can always try another 5V 386 CPU, preferably using different clock (33MHz) and probe 5V to see if its still there - will tell you if the noise comes from interposer, motherboard, cpu, clock gen or is totally independent

feipoa wrote on 2022-12-16, 12:42:

rasz_pl wrote on 2022-12-15, 07:21:

you could check what frequency 8253 channel 0 is set at (IRQ 0). Its generating DOS timer interrupt. https://wiki.osdev.org/Programmable_Interval_ … e_Current_Count

Do you have a runable DOS executable? I tried to compile that with my old Borland C++ 5.5 after adding #include <stdio.h>, and int main(void), but the compiler complained of syntax errors. I haven't programmed/compiled with Borland in over 20 years, so I gave up immediately. 😀

debug.exe should be enough?
outb(0x43,0b0000000);
EDIT: wait, this looks wrong, shouldnt it be C2?
count = inb(0x40);
count |= inb(0x40)<<8;

o 43 0
EDIT: o 43 C2?
i 40
i 40

feipoa wrote on 2022-12-16, 12:42:

Something that I don't quite understand is the core frequency on 386 systems. The CPU's CLK2 pin shows 80 Mhz and matches the oscillator installed. I see no other frequencies on the scope on CLK2. In the CPU's 1x default mode, 40 MHz, looking at the frequencies observed on VCC3, we see that the 80 MHz freq. has twice the amplitude as the 40 Mhz freq, but the 40 Mhz freq. is still present. :
FFT_1x.JPG
Where does it come from? Is it actually that all 386's simply half the incoming frequency with onboard PLL

1 bit counter, divider by 2
researchgate puts paywall unless you come from google, so to read paste this link into google and then click in google results - will load pdf
https://www.researchgate.net/profile/Avinoam- … CAD-History.pdf "Coping with the Complexity of Microprocessor Design at Intel – A CAD History"
something about designs pre Pentium using two-phase clocking scheme: "Starting at the Pentium generation, the two-phase clocking scheme was largely replaced by a single-clock and master-slave flip-flops"

feipoa wrote on 2022-12-16, 12:42:

In 2x mode, which is not the default mode on an SXL, we see that 40 MHz signal disappears and the 80 Mhz signal halves, but a 90 MHz signal of the same relative amplitude appears:
What's going on here?

cpu stops dividing so no more 40MHz. 90MHz might be some harmonic or the CPU does have pll and runs at 90MHz internally after all

feipoa wrote on 2022-12-16, 12:42:

I was also wondering if anyone had any other design suggestions for the PCB? Seems like it might be ready for a second round, assuming the price isn't ridiculous.

for the nth time - price is _$2 for 6 layer boards 5x5cm in size_ until January. This is the time to order few different versions to experiment 😀

feipoa wrote on 2022-12-16, 12:42:

What got me thinking was the layers of PCB which don't have ground between them, meaning close signal traces creating cross-talk. I was wondering for these layers if the direction of the traces matters and could be optimised? For example, should the the traces on these planes always be parallel, anti-parallel, or perpendicular? If I recall correctly, when running ethernet cables behind walls and what not, when they cross your mains, they should always cross perpendicular to reduce the interference. I was wondering if such a circumstance would apply to this PCB?

This link is all about this very topic 😀 : https://www.youtube.com/watch?v=kdCJxdR7L_I 'Do You Really Need Power Planes? Are you sure? | Eric Bogatin'

feipoa wrote on 2022-12-16, 12:42:

I was also curious if sphere swapped the layers based on rasz's suggestion, or was that undertaking too involved? Or did you think it not beneficial?

Its as good as it can in current circumstances, the only move now would be removing 5V pins and powering CPU externally from molex - this would free more space for routing and ground.

👁👅👁 mmmm external power!

you can always try another 5V 386 CPU, preferably using different clock (33MHz) and probe 5V to see if its still there - will tell you if the noise comes from interposer, motherboard, cpu, clock gen or is totally independent

I installed an Am386DX and powered up the motherboard. I took my variable DC power supply wires and attached to scope probe. The 5 Khz is still there. I tried removing the FPU, still there. But I was able to hone in on the location a bit better this time. The max amplitude of the 5 KHz signal is coming from the location of the 14.31818 MHz crystal oscillator. Curious.

1 bit counter, divider by 2 researchgate puts paywall unless you come from google, so to read paste this link into google and th […]
Show full quote

1 bit counter, divider by 2
researchgate puts paywall unless you come from google, so to read paste this link into google and then click in google results - will load pdf
https://www.researchgate.net/profile/Avinoam- … CAD-History.pdf "Coping with the Complexity of Microprocessor Design at Intel – A CAD History"
something about designs pre Pentium using two-phase clocking scheme: "Starting at the Pentium generation, the two-phase clocking scheme was largely replaced by a single-clock and master-slave flip-flops"

Nice research. I always figured the CPU was somehow halving the incoming clock. I'm not sure about early 486 boards, but later PCI 486 boards have the CLK signal coming in at the expected 1:1 FSB.

for the nth time - price is _$2 for 6 layer boards 5x5cm in size_ until January. This is the time to order few different versions to experiment :)

I'm well aware of the Chinese company's advertised end of promotion date. I've seen promotions end earlier than expected, so if it is gone before I order, I wouldn't be too surprised. Even if it is still available, there wouldn't be time to order, test, and re-fiddle the layout before a subsequent order is made. By the time alpha2 received and tested, the promotion will be over. I'm already in about $250 on prototyping (JLCPCB + components), so it is very unlikely I'm ordering alpha3 at regular rates. Thus, now is the last call for any realistic changes.

This link is all about this very topic :) : https://www.youtube.com/watch?v=kdCJxdR7L_I 'Do You Really Need Power Planes? Are you sure? | Eric Bogatin'

Thanks again, I haven't watched that video yet. If I sit and watch too many interesting videos, I get tired and don't do any tinkering. I saw that it was a 1-hr video and took a mental note for later.

Its as good as it can in current circumstances, the only move now would be removing 5V pins and powering CPU externally from molex - this would free more space for routing and ground.

For low amperage fans, I really like the idea of being able to plug the fan right into the PCB and have a fully contained unit.

debug.exe should be enough? outb(0x43,0b0000000); count = inb(0x40); count |= inb(0x40)<<8; […]
Show full quote

debug.exe should be enough?
outb(0x43,0b0000000);
count = inb(0x40);
count |= inb(0x40)<<8;

o 43 0
i 40
i 40

Maybe, don't think it liked that syntax.

1DEBUG <carriage return>
2-outb(0x43,0b0000000); <carriage return>
3  ^ Error
4- 

feipoa wrote on 2022-12-17, 09:52:

Maybe, don't think it liked that syntax. […]
Show full quote

debug.exe should be enough? outb(0x43,0b0000000); count = inb(0x40); count |= inb(0x40)<<8; […]
Show full quote

debug.exe should be enough?
outb(0x43,0b0000000);
count = inb(0x40);
count |= inb(0x40)<<8;

o 43 0
i 40
i 40

Maybe, don't think it liked that syntax.

Copy code to clipboard

1DEBUG <carriage return>
2-outb(0x43,0b0000000); <carriage return>
3  ^ Error
4- 

only 8 zeroes, bug on https://wiki.osdev.org/Programmable_Interval_ … e_Current_Count 😀

I mean those three in debug.exe
o 43 0
i 40
i 40
do the same thing

Ahh, same ^Error unfortunately with either 0 43 0 or 0 43 C2

feipoa wrote on 2022-12-17, 11:09:

Ahh, same ^Error unfortunately with either 0 43 0 or 0 43 C2

?
1:
"0 43 0" != "o 43 0", stupid fonts strike again, one of those 0 is and o and the other one is a zero
2:
o 43 0
i 40
i 40
are debug.exe commands 😀 you execute debug.exe and type them in, but that doesnt matter any more. Turns out you cant read back programmed PIT divisor and the obove only reads back current counter count while its counting down.
https://www.xtof.info/Timing-on-PC-familly-under-DOS.html :
>The only things you can really find out are the state of the lobyte/hibyte flag (this cannot be read directly, but its state can be inferred by reading the count several times, assuming the channel is being clocked)
>we cannot restore the original divisor, because we can't tell what it was.

Btw: Holy shit that blog (https://www.xtof.info/Timing-on-PC-familly-under-DOS.html) 😮 thats tons and tons of detailed minutia about every nook and cranny of PC timing architecture. "This article is a repost of a piece by Kris Heidenstrom from the mid-90s."

so lets forget that idea 😀 If you remove keyboard controller Bios will still boot a little bit and stop early in error loop before programming any timers/interrupts, if 5KHz is still there then its not from the timer. But I think it s all moot as most games reprogrammed this timer anyway. Doom definitely did
https://github.com/AXDOOMER/doom-vanille/blob … c/i_ibm.c#L1068
https://github.com/viti95/FastDoom/blob/d75ff … /ns_task.c#L138
so if its visible while doom is running its not PIT timer.

haha, I thought those were both 0's (zero's). I had also tried both O's ("ohhhh's") just in case, but not one of each.

Wow is right. I see something at 32.768 KHz (real-time clock), 1 KHz (periodic interupt from RTC), 11+ KHz (interrupt pulse-rate, from CTC), 14.31818 MHz (origin of counter/timer chip), 1.193180 MHz (/12 of CTC - counter/timer chip), 4.194304 MHz (not in PCs), 1.048576 MHz (not in PCs),

1Although the 14.31818 MHz signal is not required by modern CPUs and video cards (in fact, it is now only used for the CTC clock!), the strange frequency still hangs around like a stale fart - we are stuck with it forever. :-(

lol

Do you think the 5 KHz is an interrupt pulse ? Clearly the waveform is coming from the 14.3 MHz chip, which is the basis of the CTC. If different boards program this a bit differently, then it would explain why it isn't always the same with differnt MB's.

Did I make a mistake, or should I go into business as a fortune teller?

Or do the pieces have to be exactly 50 mm x 50 mm ?

Good chance some of the settings are slightly off without clear indication what exactly.
The tools in that page can easily do that.