Reply 20 of 35, by feipoa
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Did you have 12 ns cache to confirm that faster cache would allow for 2-x SRAM settings?
When you say "128 KB", are you using 8 chips + TAG or 4 chips + TAG, whereby 8 chips would be in interleaved mode and 4 chips would not. I have found that when pushing the limits of the memory subsystem, particularly with higher FSB's and greater SRAM quantities, that using double-banked cache (8-chips, hence interleaving) you can obtain faster SRAM timings compared to single-banked (4-chips). For this reason I never run tests single-banked.
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