VOGONS


First post, by p166s

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Hello all, I have a Packard Bell PB930 motherboard with an ALi Aladdin V chipset as described here:

930.gif
http://www.uktsupport.co.uk/pb/mb/930.htm

I recently got a K6-2+ 500/ACZM and I haven't been able to get it to POST when running at more than 450 MHz, with instability at anything above 430 MHz, no matter what voltage I use, 2.0v (from an undocumented VID) through 2.3v.
I have made a custom BIOS for it that unlocks all the available BIOS options, and I have tried various things to no avail. The one odd thing that does work, is that I can run the CPU above 450 MHz when I turn off the L1 cache first in setmul, I got it running at 570 MHz (95x6) that way even. However, if I try to re-enable the L1 cache, setmul's dos extender starts printing out SIGSEGV (crash) and then the machine hangs.

I did some research and found out that many ALi Aladdin chipset boards do not like the K6+ series, particularly the later model ASUS P5A boards.
Those boards have an M1541 Rev G northbridge, however I have a Rev E, like the older P5A models, so I wasn't entirely sure it was related until I ran speedsys.

The K6-300 is on top and the K6-2+ 500 is below it:

K6300speedsys.jpg
K62speedsys.jpg

Notice how the write cache results are abysmal for the K6-2+, it never goes above the speed of writing to main memory, even with data sizes that fit in the L1 cache.

Then I found this mod someone did to their socket:
K6-2/3+ Success on Asus P5A 1.06 - simple mod

FesterBlatz wrote:

To attempt this myself, all I did was use a 1K resistor to pull WB/WT# (pin AA5) up to Vcore 3.3v at VCC3 pin AJ19.

And then I found out what the WB/WT# pin is for, signalling to use the cache in writeback mode:

screenshot-1549702851.png
AMD K6-2E+ Embedded Processor Datasheet, Page 139, Chapter 5: Signal Descriptions, Section 55: WB/WT# (Writeback or Writethrough)

So what it looks like, is that the northbridge is not signalling the K6-2+ to use the writeback caching mode for some reason. I don't know if this will solve my inability to clock the chip higher, but given that it works until I enable the L1 cache, it might.

Does anyone here have any other knowledge to add, perhaps any BIOS modifications, that I can do to avoid having to perform any hardware mod?

Reply 1 of 1, by p166s

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Alright, so I've figured out the source of the writeback caching issue.

screenshot-1550113239.png
screenshot-1550109662.png

I never realized that it was dependent upon an MSR being set for it explicitly, and that the definition of the MSR involved with this changed between revisions of the K6 core.

screenshot-1550113208.png

vs

screenshot-1550113228.png

Initially, I was just using the CrystalCPUID MSR editing tool to set this register, but then I found a program that does this automatically on the PhilsComputerLab website.
https://www.philscomputerlab.com/k6-2-2-3-resources.html File: k6waon.zip

Here is the final result for enabling writeback caching:

K62F300combined.png

Unfortunately, this appears to have had nothing to do with my issue of achieving stability at clock speeds higher than 400 MHz.