VOGONS


First post, by melbar

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Have testet some settings on VIA MVP3.

With 512kb L2 cache and the K6-2 cpu, i want to find out the difference when 64Mb ram is installed or the double memory of 128Mb ram.
I've testet with Phil's benchmarks.

Here are the results:

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This are some of the settings, i have enabled or disabled in the BIOS. The point "Sustained 3T Write" is not available in my BIOS, but it's described in the manual.

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To summarize, i have around 0.5% to 1% difference from write-back to write-through strategy.

#1 K6-2/500, #2 Athlon1200, #3 Celeron1000A, #4 A64-3700, #5 P4HT-3200, #6 P4-2800, #7 Am486DX2-66

Reply 1 of 3, by clueless1

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Maybe I'm not connecting the dots on my own, but I'm guessing based on the info in your post that 512KB L2 can cache up to 64MB of RAM? Still, I'm not understanding how bumping RAM up to 128MB turns write-back cache into write-through cache. I guess I would've thought that if you go >64MB than either the cache only works for data in the first 64MB, or it doesn't work at all. What you're saying is the cache will work for any data in the entire 128MB, but that it reduces performance from WB mode to WT mode?

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Reply 2 of 3, by melbar

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Well, i know that the VIA chipset can cache the ram up to 64Mb, when 512 kb L2 is onboard.

As i already have told, there is this option "Sustained 3T Write" in the BIOS.
I thought that with "enabled" this function, it can be cacheable (WT) up to 128Mb.
Obviously this option is not visible in my BIOS. But in the manual it is described and visible on the picture.

Then, i have just run the benchmarks, first with 64Mb, second with 128Mb. To see what is the effect on it.

#1 K6-2/500, #2 Athlon1200, #3 Celeron1000A, #4 A64-3700, #5 P4HT-3200, #6 P4-2800, #7 Am486DX2-66

Reply 3 of 3, by elianda

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WB Caching area is limited by the Tag RAM and not by the Cache RAM.

On a 486DX2-66 WB is actually a tiny bit slower than WT as WB adds another cycle on write.
On newer systems this is better buffered and due to the higher clock speed ratio between RAM and Cache WB gains the lead.

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