jakethompson1 wrote on 2020-07-11, 18:41:
Anonymous Coward wrote on 2020-07-11, 14:18:
I don't know how your motherboard handles wait states. Usually the VLB wait state will be set by a jumper on the motherboard. Memory wait states on 486 boards are normally set in the BIOS, but I have seen some older 486 designs that used jumpers.
That's the thing, some things were faster and others were slower. It's the memory graph in the bottom right corner where the read graph, once it got past 256K, dropped to about 19MB/s for the DX2-66 and 15 MB/s for the DX2-80.
This is what made me suspicious about the 27 MHz in the top left corner.
The memory graph seems to indicate that I indeed was right about "chipset autoconfiguration" being the cause of the problem, but I explained about L2 timings, whereas the problem is in fact about main memory timing. (Nearly?) all 486 consumer boards derive the memory timing (how long to wait after the falling edge on /RAS to switch to the column address, how long to wait after that to provide the falling edge on /CAS, how long to wait after /CAS being pulled low until the data output is valid, how long /CAS needs to be low and how long /CAS needs to be high after that before the next fast-page-mode access may occur) from the main oscillator, sometimes allowing specification in half-cycles. This means the resolution for setting these time is 30/15ns with 33MHz FSB, and 25/12.5ns with 40MHz FSB. To compensate for the faster timing, the BIOS is likely increasing the number of clocks or half-clocks to keep in specification with some memory timing requirements.
As far as I know, BIOS auto-configuration on 486 boards usually tunes memory access times to be suitable for 80ns or 70ns RAM. If you have 60ns RAM installed, it is likely that the cycles counts you use at 33MHz would also work at 40MHz.
Finally, some thoughts about the numbers: 19MB/s is 1.19 cache lines per microsecond, or 840ns per cache line. This is around 28 cycles at 33MHz per cache line. 15MB/s is 0.94 cache lines per microsecond, or 1070 ns per cache line. This is around 43 cycles per cache line. The raw cycle count will be a bit lower, as the memory is also busy doing other things like refresh, but those numbers seem excessively slow for reading. Are you sure you did not mix up read timings and move timings? For moving, data is transferred twice over the bus, so speeds between 15MB/s and 20MB/s make much more sense.