Reply 60 of 67, by RayeR
I agree it may be cache flush signal. The FPGA decode bus DMA cycles and generate it. But is there any reason why it even shouldn't POST with this flush signal unconnected? I also think that 386SX should work on the module if other pins are same. Voltages as I told before are all 5V here, no regulator used. The upgrade module might be placed in socket in wrong orientation and get damaged, I don't know what anybody did with it before I got it. Currently I don't have any other SLC CPU or 386SX board for more further testing. I would also need to test the FPU in different MB or borrow 387SX to test if my MB handles it well, it behaved weird...
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