kalohimal wrote on 2024-01-11, 17:24:

4xtx wrote on 2024-01-11, 12:10:

cdd and cde are not working for me on either the eden based EPIA-ML or the c3 based PC1500 board I have.
Both are Nehemiah core

Please enable debug mode and post the result:
CPUSPD d cdd cde

..here you go 😀

My current command line usage has been:
Cpuspd m4 cd c2d cid ebd edd t10
with this, I can control everything except d-cache

If the d-cache control is implemented as "cdd/cde" is it possible your code is thinking the user is trying to use "cd"
The hint for me there is both "cdd" and "cde" appear to do what "cd" does

@4xtx

Sorry for the late reply, been rather tied up.

You're probably right, the cd and cdd/cde commands shared "cd" prefix and the parsing might be buggy. Please try this version:

(ver. 2.1 beta)

Note:
Commands moved:
For D-cache: cdd/cde => ecd/ece
For I-cache: cid/cie => eid/eie

I've not tested it and would appreciate your help to do so, thanks.

kalohimal wrote on 2024-01-15, 15:46:

@4xtx […]
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@4xtx

Sorry for the late reply, been rather tied up.

You're probably right, the cd and cdd/cde commands shared "cd" prefix and the parsing might be buggy. Please try this version:

CPUSPD.EXE (ver. 2.1 beta)

Note:
Commands moved:
For D-cache: cdd/cde => edd/ede
For I-cache: cid/cie => eid/eie

I've not tested it and would appreciate your help to do so, thanks.

Thanks very much. I will report back.

mockingbird wrote on 2024-01-15, 15:54:

kalohimal wrote on 2024-01-15, 15:46:

@4xtx […]
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@4xtx

Sorry for the late reply, been rather tied up.

You're probably right, the cd and cdd/cde commands shared "cd" prefix and the parsing might be buggy. Please try this version:

CPUSPD.EXE (ver. 2.1 beta)

Note:
Commands moved:
For D-cache: cdd/cde => edd/ede
For I-cache: cid/cie => eid/eie

I've not tested it and would appreciate your help to do so, thanks.

Thanks very much. I will report back.

Sorry for D-cache it should be ecd/ece rather than edd/ede, edd/ede are for data prefetch. Edited the previous post.

@kalohimal not sure if you saw my last post. Could you clarify what you exactly you meant with the command? Can you post the exact full command I need to enter?

kalohimal wrote on 2024-01-15, 15:58:

Sorry for D-cache it should be ecd/ece rather than edd/ede, edd/ede are for data prefetch. Edited the previous post.

Confirmed working with my Ezra-T:

Much appreciated!

@Kordanor

I'm sorry but I'm afraid there is little help I could offer beyond what had already been suggested. In your case the required hardware is either not present or not enabled, and CPUSPD can't do anything without that piece of hardware (PMU).

From what I recalled the early ALi chipsets were made prior or around the time the ACPI standard was finalized. Some of the functionalities didn't strictly adhere to the ACPI standard. In addition, for their earlier south bridges, the way the PMU is enabled and the PCI configuration registers didn't follow Intel's standard (e.g. there are additional enable bits etc.). If you'd tried THROTTLE.EXE without any luck (it was written specifically for that era of chipsets) then I debt CPUSPD would be able to help in this situation.

With that being said, there is an experimental feature in CPUSPD which allows it to read south bridge configurations from "cpuspd.sbi" file. The command to activate it is "xp" (x for experimental, so it could be removed in the future):
e.g. CPUSPD d xp t
This feature looks up the configuration entry in the config file matching the PMU id of your PC, without using any ACPI. It is similar to what THROTTLE.EXE is doing. You can give this a try, but if THROTTLE.EXE isn't working, I doubt this would too.

mockingbird wrote on 2024-01-16, 03:01:

Confirmed working with my Ezra-T:

IMG_20240115_215506400.jpg

Much appreciated!

That's great. I'll release ver 2.1 later when I find time (need to update the doc).

kalohimal wrote on 2020-08-20, 04:04:

Btw just an update on the AMD K10. I've completed coding for the multi-core setting of VID yesterday. Initial test is quite impressive: the K10 CPU I used for testing is the AthlonII x2 250, and its nominal Vcore is 1.25V. The spec is 0.85V - 1.425V, but my jaws dropped when I experimented with its Vcore and was able to set it to 0.4375V! (with FID=0 and DID=4, yielding 100MHz which is the slowest frequency possible.) Temperature drop was about 10 deg C and the heat sink was cool to the touch. And yes the system is still stable enough to play DOOM. 😊

Hi,
First of all It's nice to see you are back!
As far as I remember you were quite ready to release v2.1 with K10 support but somehow it never happened.
Since then an interesting DOS utility called SBEMU has been released so you could run DOS games on K10 even with sound using the chipset integrated sound card or an external PCI sound card (SB Live, Audigy etc.)
SBEMU: Sound Blaster emulation on AC97

So K10 is actually more relevant as a retro DOS platform than ever.
It would be great if your hard work related to K10 so far was not lost and could be released even in its current form.
Thanks in advance.

@Falcosoft

Thanks!

Ok I'll find some time to look into this. It's been so long I'd already completely forgotten what I've done. At the current moment I could do minor bug fixes but unfortunately not major changes though... hardware wise all my test rigs had been dismantled and in storage, time wise is also quite tight. But the codes should be already in there.

kalohimal wrote on 2024-01-16, 06:07:

@Kordanor […]
Show full quote

@Kordanor

I'm sorry but I'm afraid there is little help I could offer beyond what had already been suggested. In your case the required hardware is either not present or not enabled, and CPUSPD can't do anything without that piece of hardware (PMU).

From what I recalled the early ALi chipsets were made prior or around the time the ACPI standard was finalized. Some of the functionalities didn't strictly adhere to the APCI standard. In addition, for their earlier south bridges, the way the PMU is enabled and the PCI configuration registers didn't follow Intel's standard (e.g. there are additional enable bits etc.). If you'd tried THROTTLE.EXE without any luck (it was written specifically for that era of chipsets) then I debt CPUSPD would be able to help in this situation.

With that being said, there is an experimental feature in CPUSPD which allows it to read south bridge configurations from "cpuspd.sbi" file. The command to activate it is "xp" (x for experimental, so it could be removed in the future):
e.g. CPUSPD d xp t
This feature looks up the configuration entry in the config file matching the PMU id of your PC, without using any ACPI. It is similar to what THROTTLE.EXE is doing. You can give this a try, but if THROTTLE.EXE isn't working, I doubt this would too.

Thank you! Yeah, tested, and unfortunately it has no effect.
It does say:
Find PM: ISA/LPC bridge not found in c:/drivers/cpuspd/cpuspd.sbi
Don't know if that was to be expected. It changed the value to 4/8, but in 3Dbench and ChrisBench this has no effect

Ok here it is. This version includes K10 P-states control. Please note that there might still be bugs. During my testing, sometimes first few settings won't set the p-state properly and the system might reboot, and then it works after a few times (I have no idea why).
[Edit: I've since added a small delay after setting the p-state (for command pm[xx]), which seems to be stable after a few tests. More thorough testing needed.]

(Version 2.1 beta-2)

I've only tested it on 2 systems:
Biostar N68S3+ v6 with Athlon II X2 250
Gigabyte GA-770T-D3L with Athlon II X2 440

Intel's p-sate is implemented but not tested.
AMD family 15h (FX cpus, i.e. Bulldozer, Piledriver) could probably work for earlier models (00-0fh), I'd checked the datasheet and the MSR registers are similar with K10, but I'm not sure as I don't have any such systems. If you could test it out, I would be very interested to know the results.
Transmeta p-state is implemented but not tested. Please note that Transmeta cpus could only change p-state but not setting them (at least that's what appeared to be in the public docs).

P-states are the power saving states of the CPU. The higher the p-state the lower the power.
So for a CPU with 4 states:
P0 (most power/fastest) --> P3 (least power/slowest)
For AMD K10 cpu you could modify the Fid, Did, and Vid of a p-state.

P-state commands:
p[x] - display CPU p-state if run without any parameters, or switch current p-state to x, where x is 0-7 in decimal.
pm[xx] - set current CPU p-state value to xx, where xx is 0-15 in decimal for Intel, or ffddvv in hex for AMD (must be 6 digits).

Where,
ff = FID value in hex (00-3F) - Freq ID: PLL frequency multiplier relative to reference clock (6-bit).
dd = DID value in hex (00-04) - Divisor ID: post-PLL divisor to reduce the operating frequency. 00 = divide by 1, 01 = divide by 2, 02 = divide by 4, 03 =divide by 8, 04 = divide by 16
vv = VID value in hex (00-FF) - Voltage ID: voltage level (please see formula below).
For AMD, the value for the pm command must be 6 digits.

CPU voltage is calculated with this formula:
If VID >= 20h, voltage = 0.7625V - 0.0125V * (VID-20h);
else voltage = 1.550V - 0.025V * VID;

For example:
CPUSPD i p (display current p-state, it defaults to P0 when booted up)
CPUSPD p3 (switch current p-sate to P3)
CPUSPD pm00040c (edit current p-state, P3, to FID=0, DID=04, VID=0C)

To revert back to original speed is very easy, you just switch back to P0. To slow down again, switch to P3 (or whichever p-state of your choice).
CPUSPD p0 (revert to original speed)
CPUSPD p3 (slow down again)

Gigabyte GA-770T-D3L with Athlon II X2 440:

Biostar N68S3+ v6 with Athlon II X2 250:

Original speed at P0:

Switch to P3, set FID to 00, DID to 04:

Turn off cache:

kalohimal wrote on 2024-01-21, 07:45:

Ok here it is. This version includes K10 P-states control. Please note that there might still be bugs. During my testing, sometimes first few settings won't set the p-state properly and the system might reboot, and then it works after a few times ...

Hi,
Thanks, it works perfectly with my Phenom II X3/X4 CPUs. The only addition that would be nice is the "reset TSC" feature we talked about earlier. That is in case of Phenom CPUs you can reset the TSC clock to the current P0 state by toggling a bit.
With this feature added old software could also identify the valid CPU clock that is set by CPUSPD.
I have attached an example executable( and source code) that shows how this reset works. It can be used also with the current version of CPUSPD to reset TSC clock after setting a new P0 state.

Falcosoft wrote on 2024-01-21, 12:47:

Hi, Thanks, it works perfectly with my Phenom II X3/X4 CPUs. The only addition that would be nice is the "reset TSC" feature we […]
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kalohimal wrote on 2024-01-21, 07:45:

Ok here it is. This version includes K10 P-states control. Please note that there might still be bugs. During my testing, sometimes first few settings won't set the p-state properly and the system might reboot, and then it works after a few times ...

Hi,
Thanks, it works perfectly with my Phenom II X3/X4 CPUs. The only addition that would be nice is the "reset TSC" feature we talked about earlier. That is in case of Phenom CPUs you can reset the TSC clock to the current P0 state by toggling a bit.
With this feature added old software could also identify the valid CPU clock that is set by CPUSPD.
I have attached an example executable( and source code) that shows how this reset works. It can be used also with the current version of CPUSPD to reset TSC clock after setting a new P0 state.
20240121_133539.jpg
RESETTSC.zip

Ok thanks, I'll take a look. From your screenshot I spotted a bug: FID max is incorrect, it should be uint8...

@Falcosoft

Here you go. It will auto reset TSC bit if p-state 0 is modified.

(Version 2.1 beta-3)

kalohimal wrote on 2024-01-21, 16:05:

@Falcosoft

Here you go. It will auto reset TSC bit if p-state 0 is modified.

(Version 2.1 beta-3)CPUSPD.EXE

Thanks, it works!

I've tested it on the Eden and can say it now works correctly.
Thank you and I will make an update to my video 😀

kalohimal wrote on 2024-01-15, 15:46:

@4xtx […]
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@4xtx

Commands moved:
For D-cache: cdd/cde => ecd/ece
For I-cache: cid/cie => eid/eie

I've not tested it and would appreciate your help to do so, thanks.

4xtx wrote on 2024-01-22, 07:28:

I've tested it on the Eden and can say it now works correctly.
Thank you and I will make an update to my video 😀

Thanks for the update!

Found a little time to experiment with AMD Zen 2 CPU (specifically Ryzen 5 3500X) + Asrock B550M-HDV.

I was able to set frequency down to 200MHz, but there are a few issues:

1. Could only change to p-state 0 & 2 but not 1. Not sure why. Checking the MSR shown that the proper p-state was requested, but the cpu just refuse to go to p-state 1.
2. Working properly under JEMMEX v5.84 and I was able to modify the p-state, except item above. But I couldn't get SBEMU + JEMMEX to work on this system. JEMMEX loads fine, but as soon as SBEMU is loaded, an exception fault will occur after a few key strokes. No SBEMU means no sound.
3. At 200MHz with cache disabled, it was running at around Pentium -133 speed and still a little too fast for Wing Commander. There isn't other way to further slow down the cpu frequency, so 486 and slower speeds are out of reach.

Conclusion: Doesn't look too promising.