Of course the 80286 processor can interact with 8-bit hardware, as we see every time an 8-bit VGA card is installed in an AT compatible computer. But that only works because the chipset translates the 16-bit cycle into 2 8-bit cycles. The 80286 processor itself has the following properties:

• Instruction fetches are always 16 bits
• If it requests a 16-bit cycle (BHE high, A0 low), it expects all 16 bits to be handled before READY is asserted
• 8-bit transfers from/to odd addresses are requested using BHE high, A0 high, and must transfer data on D8 to D15

While you can avoid 16-bit data cycles directly created from your program by never accessing properly assigned 16-bit words using 16-bit instructions, at least instruction fetches are always performed using 16 bits, no matter what you do. (You can misalign the stack, to have the '286 split all stack access cycles into 2 8-bit cycles, you might be able to do the same for the IDT, so you might get away for data) So for a pure 8-bit system, you need to

• provide a path from D8-D15 to D0-D7 on the bus.
• provide a way to disconnect D0-D7 of the processor from D0-D7 on the bus.
• split 16-bit write cycles into two 8-bit write cycles, one using D0-D7, the other using D8-D15. You need to sequence these cycles yourself.
• split 16-bit read cycles into two 8-bit read cycles, latching the result of the first read, to be able to present the 16 bits at once to the processor.
• forward 8-bit accesses to odd addresse (BHE high) to the low address bits.

The IBM AT has logic to accomplish the items of the previous list on its mainboard, and that's why the 8-bit XT expansion cards work in the IBM AT.

Thanks for the reply.

I think you have a slight mistake there, If I checked the manual correctly:

BHE=0 and BLE=0 >>> 16bit transfer
BHE=1 and BLE=0 >>> 8bit transfer via D0-D7
BHE=0 and BLE=1 >>> 8bit transfer via D8-D15
BHE=1 and BLE=1 >>> this is invalid signal, doesn't happen

Are you saying that, for pure 8bit system (except cpu of course), I need some kind of controller and latches to handle 16bit transfers?

I checked the chips on IBM AT and can't see which of them could be doing this.
Surely not the 82288 I think ?
So how does IBM AT does this ?

If it really not possible to do by "simple" means then too bad.
I was really wished that it was possible.

Edit: Also, in fact 80286 does a 16bit transfer using 2x 8bit transfers, natively, but only if trasferring a word to (not from!)an address that starts with odd.
Already so much complication but not very useful for a system designer, what were they thinking when designing these cpus.
Would be really nice to have a "286sx" with native 8-bit data bus.

There is IBM XT/286 also.

It only has 8Bit Slots.
Maybe you can look at the Service Manuals.

matze79 wrote on 2020-08-18, 11:29:

There is IBM XT/286 also.

It only has 8Bit Slots.
Maybe you can look at the Service Manuals.

100% false. I have one. It has 3x 8bit slots and 5x 16bit slots

PlaneVuki wrote on 2020-08-18, 11:26:

Thanks for the reply. […]
Show full quote

Thanks for the reply.

I think you have a slight mistake there, If I checked the manual correctly:

BHE=0 and BLE=0 >>> 16bit transfer
BHE=1 and BLE=0 >>> 8bit transfer via D0-D7
BHE=0 and BLE=1 >>> 8bit transfer via D8-D15
BHE=1 and BLE=1 >>> this is invalid signal, doesn't happen

That's the 386SX bus interface, which is often believed to be identical to the 80286 bus interface. It is not identical! The 80286 does not have a BLE signal, but it has an A0 signal instead. It uses the following table:

A0=0 and BHE=1 >>> 16bit transfer
A0=0 and BHE=0 >>> 8bit transfer via D0-D7
A0=1 and BHE=1 >>> 8bit transfer via D8-D15
A0=1 and BHE=0 >>> this is invalid signal, doesn't happen

PlaneVuki wrote on 2020-08-18, 11:26:

Are you saying that, for pure 8bit system (except cpu of course), I need some kind of controller and latches to handle 16bit tra […]
Show full quote

Are you saying that, for pure 8bit system (except cpu of course), I need some kind of controller and latches to handle 16bit transfers?

I checked the chips on IBM AT and can't see which of them could be doing this.
Surely not the 82288 I think ?
So how does IBM AT does this ?

The technical reference manual for the 5170 is available on minuszerodegrees, schematics of the AT mainboard ("planar") type 1 start at page 92 (linear page count) aka page 1-76. Central components are

• the registered bus transceiver 74LS646, U67, on sheet 2 (it can latch the low 8 bits)
• the PAL 16L8, U87 on sheet 6 (generates the control signals)
• the transceiver 74LS245, U102 on sheet 13 (it forwards low-to-high or high-to-low on the system bus)
• the logic on the lower half of sheet 12, involving DATA CONV, CONVA0 and CONVALE. This logic uses clocked flip-flops to sequence the two sub-cycles.

PlaneVuki wrote on 2020-08-18, 11:26:

If it really not possible to do by "simple" means then too bad. I was really wished that it was possible. […]
Show full quote

If it really not possible to do by "simple" means then too bad.
I was really wished that it was possible.

Edit: Also, in fact 80286 does a 16bit transfer using 2x 8bit transfers, natively, but only if trasferring a word to (not from!)an address that starts with odd.
Already so much complication but not very useful for a system designer, what were they thinking when designing these cpus.
Would be really nice to have a "286sx" with native 8-bit data bus.

All word cycles to odd addresses (misaligned word cycles) get split by the 286, both reads and writes. I already alured to that in my previous post by suggesting a misaligned stack to prevent 16-bit operations from happening. In the Am80286 datasheet, it is written on page 1-96, below the head-line "Physical Memory and I/O interface", bold-face emphasis mine:

80286_Datasheet wrote:

...while odd-addressed words require two bus operations. The first transfers data on D15-D8, and the second transfers data on D7-D0. Both byte data transfers occur automatically...

PlaneVuki wrote on 2020-08-18, 11:26:

Would be really nice to have a "286sx" with native 8-bit data bus.

Take a look at the 80188, if you don't need protected mode. There are embedded 80188 variants available today that use 256 byte segment spacing instead of 16 byte segment spacing, such that the addressable range is 16MB, just like on a 80286.

Yeah seems i was mistaken, it was Siemens 80186 or 88 System then..
somewhere i have some odd SBC

The Idea of getting some sort of 80288 CPU... intriguing... 😀

waterbeesje wrote on 2020-08-18, 16:18:

The Idea of getting some sort of 80288 CPU... intriguing... 😀

I’m sure a 80288XT2 overdrive chip would have been popular back in the day

waterbeesje wrote on 2020-08-18, 16:18:

The Idea of getting some sort of 80288 CPU... intriguing... 😀

A 80288 is not that of a bad idea. The 80286 bus can do a 0WS memory access in two clocks, whereas the 8086/80186 needs four clocks per bus access. The 80188 was severely limited by it's low memory bandwidth. Give it a double-speed bus, and it might rise to its full performance level.

An FPGA board could likely be designed to replace an 8088 with a core like a 286 (or 386).

The ideas are all very interesting, IMHO. I'm just curious: Why is a single 8-Bit RAM required ?
- Two 8-Bit RAMs in tandem could be used without any trickery. And it will double capacity, as well.

Edit: Maybe also useful: http://faculty.ksu.edu.sa/sites/default/files … interface_0.pdf