I picked up a Biostar MB-8433/40UUC-A a while back. This board is like a cross between an early Shuttle HOT-433 and a Biostar MB-8433UUD-A. It has an early revision UM8881F and UM8886AF chipset.

Like the MB-8433UUD-A it has two cache banks, one with 32-pin sockets and one with 28-pin. The board has 512K single-bank settings printed on it, but the two jumpers needed to be set to bump it from 256K single-bank to 512K single-bank were missing. Someone asked about that eight years ago: MB 8433/40 UUC Jumper option soldering

Happy to report that by soldering on those two missing jumpers so they can be set, and acquiring some of the sketchy IS61C1024-10N cache chips, it seems to be working stable at 33 MHz, 2-1-1-1 cache read timing, and 0 WS write timing. I've tried various things to verify stability including HIMEM's test (which was more effective than I expected), Memtest86, and compiling a Linux 2.2 kernel which historically was much more aggressive at bringing out stability problems on 486 hardware than DOS.

I had one cache chip that passed the test in the TL-866 II, but wouldn't work at 2-1-1-1 on this board. I determined it was one bad chip because HIMEM would always fail on an address ending in either 6, or E.

As others, especially Feipoa, have posted previously, whether "aggressive" cache settings work reliably also depends heavily on how many and what brand of SIMMs are installed. In my case, a single 64MB SIMM is so unstable that HIMEM fails, but a pair of 32MBs works. That's interesting as usually it's the opposite. To the EEs and CompEs out there, I'm not heavily into hardware so I'm curious to hear any speculation about this. The SIMMs and cache chips are all driven by the cache controller's address outputs, right? Is the issue that some SIMMs draw more current or have more capacitance than others, slowing down the cache chips' ability to "see" the new address? Or, is it something with the SIMMs being too slow to "release" the data lines after a DRAM access?