I've been trying to figure out what, if any pins the IBM 486SLC2 uses in addition to what is in the 386SX standard. I don't have one handy right now, because I'm traveling. However, I did figure out something interesting about how the cache works, from the OPTi 82C295 chipset datasheet, which has support for the cache. On the 386SX, the ADS# is output only, and asserted by the processor when all of the pins have been set up properly for a bus transfer. It turns out that on the IBM 486SLC2, this pin is I/O. The chipset asserts it during a DMA cycle, and the 486SLC2 uses this as a hint to snoop the WR#/MIO#/address signals to know whether it needs to invalidate an entry in the cache. So it looks like no additional pins are required for the CPU cache, but, the chipset controller has to be capable of asserting the pins connected to ADS#/WR#/MIO# on the CPU in order for it to properly snoop the cache and invalidate entries.

What is strange is that the chipset is compatible with the 386sx, the IBM 486SLC2, and the Cyrix Cx486SLC - which does have special pins to control the cache, but there is no configuration for "chip type" in the chipset - either by pin or by software. So, this would seem to imply that it always asserts these pins, even on a 386SX or a Cyrix Cx486SLC, that it always asserts the special Cyrix pins, and that perhaps on the Intel and Cyrix chips, these internally float when not in use, even though they are output only?