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Can't get into CMOS setup on old 486.

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Reply 60 of 68, by jakethompson1

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Keatah wrote on 2021-06-13, 08:24:

In effect I suppose the improperly configured cache made the first 64K work incorrectly. This was also mentioned earlier the discussion - BIOS was never able to proceed far enough.

Interesting. I'm surprised it wouldn't give you the opportunity to enter CMOS setup before enabling the external cache. It does seem like these old Phoenix BIOSes are from the 8086/286 era and just barely had enough features added to work with a 486. The newer Phoenix BIOS (4.x) was acquired from Quadtel, I think.

Reply 63 of 68, by Keatah

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According to the Phoenix BIOS Reference Book the external cache controller is almost last to tested or initialized. It doesn't say anything about the testing the cache memory. I'm inclined to believe it just checks for the presence or absence of the controller and maybe a "ready" signal of some sort.

Additionally the pinouts for 8 x 8 vs 32 x 8 SRAM chips are different. With slightly different arrangements of the upper address lines and the CE signal. I will also guess that jumpers on the motherboard change how those signals are routed. I believe the DIP switches change the interleave. With the 128K configuration not having any interleave at all since it uses only uses 4 SRAM chips in Bank0, 32 x 8.

The 64K and 256K configs allow for interleave because they're using both Bank0 and Bank1. 8 chips for each of those configs.

This board is delightfully primitive in that it offers no accoutrements. No integrated peripherals. No hi-speed bus anything. No extra services beside an L2 cache. There's no autoconfiguration of anything. And no power management. It's one step above a 386. 1 narrow step. No real upgrade path except maybe a certain Intel Overdrive chip, or maybe the AMD based AM5X86.

But it does have a luxurious set of 8 16-bit ISA slots. And moderately flexible RAM configs.

Reply 64 of 68, by Caluser2000

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Keatah wrote on 2021-06-13, 22:24:
*SNIP* […]
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*SNIP*

This board is delightfully primitive in that it offers no accoutrements. No integrated peripherals. No hi-speed bus anything. No extra services beside an L2 cache. There's no autoconfiguration of anything. And no power management. It's one step above a 386. 1 narrow step. No real upgrade path except maybe a certain Intel Overdrive chip, or maybe the AMD based AM5X86.

But it does have a luxurious set of 8 16-bit ISA slots. And moderately flexible RAM configs.

Aaaaah, life was much simpler back then 😉

There's a glitch in the matrix.
A founding member of the 286 appreciation society.
Apparently 32-bit is dead and nobody likes P4s.
Of course, as always, I'm open to correction...😉

Reply 65 of 68, by Keatah

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mR_Slug wrote on 2021-06-13, 19:33:

Can we use your picture to document the board here: http://www.win3x.org/uh19/motherboard/show/3716

Yes of course.

Additionally here is the Micronics M810 memory card, which provides an additional 32MB via Bank2 and Bank3. 64MB system total. You may also use this photo.

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Reply 67 of 68, by Keatah

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One other brief note. Your site lists the optional numeric processor as a 3167. This is a 486, so it would use the Weitek 4167..

Many years ago I saved this from this: http://support.mpccorp.com/tech_support/MOTHE … 3/00000005.html

Last Modified: 11/15/2003, Author: TCM, Revision: 1.01

Chipset
4000053,GEM486-33,GEM486-33F

The Micronics Gemini chipset consists of a MIC 461 Cache/Memory controller and a MIC 462 AT controller. The Micronics Gemini chipset was designed for use with all current (at that time) 80486 based architecture. It supports processor speeds of 20, 25, 33, and 50 megahertz (MHz). It supports up to 256 kilobytes (KB) of direct-mapped, secondary cache. It features zero wait states for read-in burst or non-burst modes. It also features zero wait state power-on self-test (POST) memory write. It supports 256 KB ´ 9, 1 MB ´ 9, and 4 MB ´ 9 Dynamic Random Access Memory (DRAM) modules up to 64 megabytes (MB) of memory. It supports the Weitek math co-processors. It has built-in parity generation, port B registers, and refresh logic.

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